White Paper: Setting up a Versatile Flow & Environment to Improve Design Productivity
Today’s chip designers need to handle numerous and well-documented technical challenges associated with advanced process nodes, such as signal integrity and timing closure, leakage power management, functional verification, DFT integration and advanced physical design methodology for manufacturability and yield. However, survey data shows that design teams are also simultaneously dealing with significant and growing project-related challenges beyond the characteristics of the specific design itself, such as inconsistent design development across geographically distributed design teams, the ramping up of new sites, and correcting issues with 3rd party library and IP quality.
Modern design flows must handle all of these challenges and still provide more flexibility, greater modularity, and new methodologies for achieving predictable design tape-outs. To meet these goals, an enhanced design flow must be more than a means to solve design problems. It must also improve designer productivity and make IC design organizations more competitive.
This white paper outlines a production design flow and environment that leverages the experience of Synopsys Professional Services designers, a design organization that participates in dozens of customer tape-outs each year at a variety of process nodes. Because Synopsys customers use many different foundries and libraries, implement a wide range of design applications, support multiple points of design handoffs, and commonly function with distributed teams, our design consultants encounter the full spectrum of design- and project-related challenges of mainstream and advanced chip development.
Click here to see an outline of the paper.