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White Paper: Power Hungry? Strategies to Trim Your Chip’s Appetite
Part 1: Overview, Analysis, Architectural Solutions
Rapid changes in SoC power consumption have forced designers to rethink the methodologies they employ throughout the design flow to account for power-related effects. In addition to leakage power impacting battery life in mobile applications, increases in SoC size and speed have brought heat dissipation and reliability issues such as electro-migration and IR drop to center stage in virtually all chip designs at advanced process nodes.
This FREE white paper, from Synopsys Professional Services, is Part One of the two-part series that provides an overview of the topic of SoC power management and describes methods for estimating and analyzing power consumption. Using insights from a pool of industry talent, including Synopsys R&D engineers, consultants, and customers with design experience at 90nm, 65nm, and 45nm, Part 1 of this series provides a full description of power-related issues and the requirements for early power planning, starting at the architectural level. Part 2, to be subsequently published, will describe details of power-management methods, with an emphasis on the growing importance of leakage power in SoCs.
To see the outline for Part 1, click here.
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