System-Level Design

China 简体中文 Japan 日本语 United States English
International Office Locations

By Design Phase


System-Level Design High-level block design, architecture design, virtual and FPGA-based prototyping, and, power electronics and wiring harness solutions		Manufacturing Mask synthesis and data prep, lithography simulation and verification and yield management

Verification High-performance system, RTL, equivalence checking, mixed-signal verification solutions, and Verification IP		TCAD Process and device simulation solutions for technology development and manufacturing

Implementation & Sign-Off Advanced digital and custom IC and FPGA design solutions, including synthesis, physical implementation, test and sign-off		Optical Design Optical design and analysis software and engineering services All Tools Directory of all Synopsys tools

Reduce Risk with High Quality IP


Interface IP Standard interfaces for SoC designs such as USB, PCIe, DDR, SATA, HDMI, MIPI and more		Logic Libraries SiWare Logic and ASAP Logic standard cell libraries for a wide array of applications and process technologies

Analog IP Analog IP such as audio codecs, data converters and video analog front-end		Processor IP ARC Processor Cores, ARC Sound family, ARC Video family and configurable extensions

Embedded Memories Embedded memory solutions including embedded SRAMs, embedded non-volatile memory and embedded test and repair		SoC Infrastructure IP minPower Components, Verification IP and the DesignWare Library including datapath IP, AMBA, foundry libraries and 8-bit microcontrollers

Unmatched productivity from System to Implementation


High-Level Block Design Rapidly create and optimize differentiated IP blocks with Algorithm Design and Analysis, High-Level Synthesis, and Processor Development		Virtual Prototyping Accelerate pre-RTL embedded software development, hardware/software integration, and system validation

Architecture Design Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design		FPGA-Based Prototyping Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow

Power Electronic Systems Simulate and execute behavioral design, modeling, and simulation for power electronics, multi-domain systems, and wire harnesses		System-Level Models Reduce risk and speed time to market with pre-verified models supporting industry standards for interoperability

Helping You Address Your Toughest Design Challenges


Tool and Methodology Adoption Take full advantage of the latest features and methodologies available in Synopsys' tools		Design Implementation Leverage tapeout-proven flows and project experience to get your chip done

SoC Design & Verification Achieve rapid design closure by applying best practices in system-level design, RTL creation, FPGA-based prototyping, and functional verification		Low Power Optimization Implement low power implementation and verification techniques to optimize your chip's power consumption

Design Flow Deployment Optimize your design flow to address the latest design challenges		Predictable Silicon Sign-Off Improve ASIC handoff with early optimization for physical effects

Solutions for Semiconductor and System Design


End-to-End Solutions Comprehensive solutions: Eclypse Low Power Solution, System-to-Silicon (S2S) Verification Solution		Technical Platforms Integrated product platforms: Discovery Verification Platform, FPGA Design Solution, Galaxy Implementation Platform

Industry Solutions Tailored solutions for automotive, memory, mil/aero, mobile devices, & end-product categories		Lynx Design System A highly integrated, production-ready IC development platform

Expert Training and Support Services


Training Training courses on Synopsys� tools and methodologies		Global Support Centers Open a support issue online

SolvNet Get instant online access to the self-help support resources you need		Licensing, Installation & Compute Platforms The latest information about how to install, upgrade and manage your Synopsys licenses

Explore, Interact and Collaborate


Synopsys Users Group (SNUG) Technology users and product experts exchange ideas at SNUG conferences		University Program Resources for teaching IC design: how to apply to our program, curriculum, articles, support and training, and much more

Partners Collaborating to provide advanced reference flows, design kits, libraries, IP and methodology		Interoperability EDA tools working together for customer satisfaction and success

Blogs & Forums Insights from the experts, open forums for global Synopsys community		Conversation Central Join us the third Thursday of each month to join the conversation!

Synopsys: Innovation and Beyond


About Synopsys Discover our company, our management team and our values		Synopsys Careers Learn about jobs, internships and our commitment to diversity

News Room Read Synopsys news, contact the PR team, download an image, or gather other information		Events Meet with Synopsys at an industry event, participate at a SNUG® conference , or attend a Synopsys workshop or seminar

Investor Relations Browse information for shareholders, analysts and potential investors		Community Involvement Learn how Synopsys inspires the next generation of technologists

HOME

SYSTEMS

VIRTUAL PROTOTYPING

SCML Source Code Kits

The SystemC Modeling Library (SCML) is a standards-based, TLM-2.0 compatible API library that eases the creation of user-defined SystemC TLM peripheral models for use in Synopsys Virtual Prototypes. A source code implementation of the SCML API library is openly available. Its purpose is to protect user investment in user-defined SCML peripheral models by enabling their use in other IEEE 1666 SystemC compatible simulation environments, and to enable discussion on the requirements for standards. To download, please select a kit then click the 'Continue >>' button below.

Select your kit:

	SCML Source Code Library v2.1.1 with TLM-2.0 Loosely-timed PV examples
	Content Includes: SCML Source Code API library 5 SCML peripheral examples for confirming user-code portability between IEEE 1666 SystemC environments and illustrating model interoperability using the OSCI TLM-2.0 Loosely-timed and TLM 1.0 PV Transport API Standards Includes sample build scripts to run the examples in OSCI/gcc 3.4.4, gcc 4.2.2 and msvc-9.0 SCML API documentation TLM Peripheral Modeling white paper
	SCML Source Code Library v2.1.1 with TLM-2.0 Loosely-timed PV examples combined with Architect's View OCP TL2 communication*
	Content Includes: The same SCML Source Code Library v2.1.1 with TLM-2.0 Loosely-timed PV examples kit as shown above (you don't need both kits) Adds OCP-IP TL2 SystemC channels and PV/OCP transactors Confirms portability and illustrates model interoperability at two levels of abstraction using the OSCI TLM-2.0 Loosely-timed and TLM 1.0 PV Transport API Standards, the OCP-IP TL2 SystemC channels, and PV/OCP transactors *Because it includes SystemC source code for OCP TL2 channels provided by OCP-IP, membership in OCP-IP is required to download this kit. If you're not yet an OCP-IP member, you can learn more and apply for membership. (OCP-IP Participant memberships are available at no charge.)