FPGA Design 

Best Quality of Results and Fastest Tool Flow to Deliver Any FPGA Design 

Synopsys’ FPGA design solution is a comprehensive suite of tools that deliver the industry’s best results for both timing performance and area optimization. This suite is comprised of Synplify® synthesis, Synphony Model Compiler for DSP design, Certify® enabling multi-FPGA partitioning, and Identify® RTL Debugger. The combination of these solutions provides designers with the necessary tools to delivery any FPGA based design to market faster and with the best quality of results required for today’s complex FPGA designs.

Synplify® synthesis delivers world class technology for fast synthesis algorithms, along with multi-processing, hierarchical and incremental design technologies that enable designers to achieve timing closure with the highest productivity rate. Synplify® synthesis coupled with Identify® RTL Debugger provides developers with a powerful methodology to instrument and debug their RTL to deliver differentiated product to market faster.

Synphony Model Compiler (SMC) provides a comprehensive, high-level model library for creating math, signal processing, and communications designs in the Simulink® environment. This enables designers save months in design and verification of signal processing hardware and systems with signal processing IP, best QoR across any technology and high-performance verification.

To learn more about Synopsys' FPGA design tools, read the whitepapers or download a FREE product evaluation of Synplify.

  • Design Tools

Synplify Pro
Logic Synthesis for FPGA Implementation
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Synplify Premier
Fast implementation of advanced FPGAs and FPGA-based prototyping
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  • FPGA Debug Tools
  • Integrated RTL debug and visibility enhancement 

Identify RTL Debugger
Simulator-like visibility into FPGA hardware operation
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Uses Xilinx Virtex®-7 FPGAs for capacity up to 4 million ASIC gated
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Uses Xilinx Virtex®-7 FPGAs for capacity up to 288 million ASIC gates
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Design automation and debug for the HAPS Series
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Multi-FPGA implementation and partitioning
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  • DSP Design
  • High-level synthesis and accelerated verification for signal processing  

Synphony Model Compiler
Faster, More Efficient ASIC & FPGA HW Development for DSP Algorithms
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  • High-Level Synthesis
  • High-level synthesis from language and model-based designs 

Synphony C Compiler
High-level synthesis to accelerate design of image processing IP
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  • Design for High-Reliability
  • High-reliability FPGA solutions including DO-254 support 

High-Rel Solutions
Synopsys design for high-reliability
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DO-254 Compliance
DO-254 Solution for airborne electronics
PDF Download Datasheet (PDF)

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