Synopsys software-defined ZeBu® emulation systems deliver the performance needed to make verification teams and software developers working on the most advanced chips successful. ZeBu emulation systems are modular, allowing users to deploy the capacity needed in a scalable and easily extensible fashion.
The Synopsys ZeBu® Server 5 emulation system delivers 2X the emulation performance and 2x higher throughput compared to its predecessor, to enable SoC verification and software bring-up, and to address the exploding verification requirements of automotive, 5G, networking, artificial intelligence, and datacenter SoCs.
While extending design capacity to up to 23 BG, the Synopsys ZeBu-200 software-defined emulation system also offers up to 2X higher runtime performance vs. the previous generation ZeBu EP with faster compile time, reducing turnaround time and enhancing development productivity.
Synopsys ZeBu EP is a scalable unified hardware platform for emulation and prototyping. It has high performance and capacity scaling to validate long software workloads for billion+ gate designs.
ZeBu-200 is built on the Synopsys EP-Ready Hardware Platform that allows for software-defined upgrade to support HAPS-200 asynchronous clocking and HAPS ProtoCompiler, as well as the compliance and certification use case. Read more in our blog.
Users tend to do a lot of targeted functional verification as the RTL starts to come together. They need a platform that makes it easy and quick to port over their simulation environments and provide enough acceleration to cover the scenarios that are not ideal for simulation and formal environments. ZeBu’s simulation acceleration capabilities are utilized by industry’s major GPU, CPU, NPU, TPU providers along with other IP vendors in the networking, automotive sectors.
As RTL matures, users desire a platform that can provide orders of magnitude faster performance to cover long running suites. These regression suites serve the dual purpose of proving functional correctness, as well as getting closer to targets for coverage metrics. ZeBu’s transaction-based high-performance platform combines with its strong suite of industry’s latest Protocol Solutions (Transactor and Speed Adapters) to address these needs at some of the largest chip companies.
Starting from a reasonable level of RTL maturity, users start bringing up their software environments. There is a mix of bare-metal, low-level drivers and firmware, operating systems like Linux-Windows-Android, benchmark software application, general-purpose user applications that need to be brought up and proven functional. As the user persona evolves from being hardware-centric to a mix of hardware and software, ZeBu brings capabilities like Virtual Host Solutions to make the software developer feel at home. Combined with its superior performance, users can get very close to silicon like behavior.
As the designs near tape-out schedules, validation engineers get into a mode of mimicking their post-silicon lab environments. Their primary requirement is to enable hardware and software developers with a platform that could be used to serve as the highest-performance option in pre-silicon testing using real-world interfaces. They also want to build this platform as an option to reproduce and debug issues that they would encounter in the lab. Visibility into the design and being able to deterministically repeat those scenarios is key. ZeBu comes with a suite of strong debug technologies as well as a wide suite of speed adapters that have proven a capable partner for users to identify bugs and resolve them timely to not impact the customer’s time-to-market.
Users turn their attention to key design attributes of power and performance. They have long-running workloads that heavily exercise the DUT. By design, ZeBu can accurately model large number of clock domains prevalent in the modern SoC environments and yet provide the performance to execute these workloads.
The ZeBu solution for Arm SBSA compliance enables running the Arm SBSA test suites and quickly identify non-compliant HW issues. SBSA compliance ensures that any software that has been compiled for the specific Arm architecture will run on the silicon being designed and verified with the SBSA compliance solution.
Synopsys Hardware-assisted Test Solutions are advanced stimulus generation and checking tools for the most difficult verification problems. HW-assisted Test Solutions maximize the ability to find critical bugs before a design reaches silicon, achieving compliance with the intended architecture.
".... Synopsys’ software‑defined hardware‑assisted verification and the new HAPS‑200 12 FPGA systems are accelerating our system‑level verification and validation, helping us deliver complex AI platforms on aggressive schedules. And Synopsys modular hardware-assisted verification enables deeper collaboration across our ecosystem."
Narendra Konda
|Vice President, Hardware Engineering, NVIDIA
“... HW-assisted verification is no longer optional. It is critical to meeting aggressive time-to-market goals and ensuring silicon readiness. FPGA-based emulation and prototyping play a central role in that effort by accelerating system bring-up and enabling earlier software development... Through joint optimization of Synopsys ZeBu with the AMD Vivado software stack, and by leveraging AMD EPYC processors for compute acceleration, we are reducing compile times and helping customers move to accurate system models faster.”
Salil Raje
|Sr Vice President and General Manager, Adaptive and Embedded Computing Group, AMD
*Based on AMD internal analysis in May 2023 with a 6-input LUT count to compare the Versal Premium VP1902 device versus competitor offerings.
“Synopsys is a key member of Arm Total Design, bringing critical tools and the advanced HAV capabilities to quickly and reliably validate solutions built on Arm Compute Subsystems (CSS). The new ZeBu-200 and HAPS-200 hardware platforms will also assist our mutual customers in integrating Arm CSS into their designs with improved turnaround times to meet the demanding requirements for complex data center infrastructure and automotive systems.”
Kevork Kechichian
|Executive Vice President, Solutions Engineering, Arm
“Verifying hardware for our highly anticipated rack-scale AMD Helios solution... demands scalable and versatile verification platforms. The Synopsys SW-defined, HAV capabilities with EP-Ready hardware are critical to how we perform CPU, GPU and AI subsystems verification as well as full-system validation... "
Alex Starr
|Corporate Fellow, AMD
“SiFive has a very large and configurable portfolio of RISC-V CPU and AI core IP. We extensively test our IP using software workloads on HAPS, which means we can run trillions of cycles per day. As next generation CPUs and AI cores become larger and more complex, we need to efficiently map them onto larger and more powerful FPGAs. With its EP-Ready hardware HAPS-200 offers us an FPGA platform to do full system emulation for reference platforms that scale from small microcontrollers all the way to large scale data center designs.”
Albert Huntington
|Vice President, Platform Engineering, SiFive
"AMD has used ZeBu EP solutions for fast emulation with software workloads for a number of years. The EP-ready Hardware concept has allowed us to switch on demand, as a design matures, to a prototyping use case and significantly increase workload throughput. ZeBu-200 and HAPS-200 EP-Ready systems will enable further performance improvements to accelerate design verification and software validation."
Alex Starr
|Corporate Fellow, AMD