DesignWare ARC Processor Cores 

Accelerating Development of Performance-Efficient SoCs 

Synopsys' DesignWare® ARC® Processors are a family of 32-bit CPUs that SoC designers can optimize for a wide range of uses, from deeply embedded to high-performance host applications in a variety of market segments. Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements. The DesignWare ARC processors are also extendable, allowing designers to add their own custom instructions that dramatically increase performance. Synopsys' ARC processors have been used by over 170 customers worldwide who collectively ship more than 1 billion ARC-based chips annually.

All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent performance and code density for embedded and host SoC applications. The RISC microprocessors are synthesizable and can be implemented in any foundry or process, and are supported by a complete suite of development tools.

DesignWare ARC processors are supported by a variety of 3rd-party tools, operating systems and middleware from leading industry vendors, including members of the ARC Access Program.

PDFDesignWare ARC Processors Portfolio Brochure

 
  • ARC HS Family
  • High-speed, 32-bit multicore processors for high-end embedded applications more

ARC HS34
Single-, dual- and quad-core 32-bit processor for real-time control applications


ARC HS36
Single-, dual- and quad-core 32-bit processor with I and D cache


ARC HS38
Single-, dual- and quad-core 32-bit processor for embedded Linux applications


ARC 710D
Cacheless 32-bit processor for real-time control


ARC 725D
Efficient 32-bit processor with I & D caches


ARC 770D
High-performance processor with MMU and Linux acceleration package


ARC 601
Compact, low-power, cacheless 32-bit processor


ARC 605
Compact, cacheless 32-bit processor with power management unit


ARC 610D
Low-power, cacheless 32-bit processor with DSP capabilities


ARC 625D
Low-power, 32-bit processor with DSP capabilities and I & D caches

  • ARC EM Family
  • Compact, ultra low-power processors for deeply embedded applicationsmore

ARC EM4
Ultra-compact and power-efficient cacheless 32-bit processor


ARC EM6
Ultra-compact and power-efficient 32-bit processor with I & D caches


ARC EM5D
Compact, power-efficient DSP-enhanced processor with I & D CCMs


ARC EM7D
Compact, power-efficient DSP-enhanced processor with I & D CCMs and caches


ARC EM SEP
EM4 with Safety Enhancement Package for automotive applications


 
Configurable audio processors for low- to high-end applications


ARC Memory Protection Unit
Division of address space into regions associated with specific attributes such as read, write, and execute prevents faulting instructions from completing


ARC Secure
Execution of encrypted code for ARC 600 cores provides cost-effective protection against memory and system attacks with little impact on system performance


ARC XY Advanced DSP
Adds the power of a true DSP engine to enable conventional and signal processing computation within a single architecture


ARC Floating Point Options
Adds high-performance single- and double-precision floating point math instructions to ARC processor families


ARC Real-Time Trace
Hardware modules that can be integrated into any ARC-based SoC to enable rapid software debug with minimal increase in die size and no power consumption penalty


ARC Audio Processors
High-performance audio processors with low power consumption and small footprint for a broad range of SoC designs


ARC Audio Codecs
Ideal for ultra-low power portable applications or for high performance broadcast and home entertainment SoCs


Media Streaming Framework
For easy creation of complex audio graphs, including a Blu-ray Disc reference design

Synopsys' broad portfolio of DesignWare® ARC® Processors includes a variety of 32-bit CPUs from power-efficient to high-performance cores that SoC designers can optimize for a wide range of uses, including embedded and deeply embedded applications. Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet the specific performance, power and area requirements of their mobile, IoT, digital home, automotive, industrial and storage applications.

Mobile
Mobile

High-performance ARC multicore processors have excellent DMIPS/mW for battery-operated mobile apps

more
  Internet of Things
Internet of Things

On-chip integration of sensor control, embedded processing & communication for IoT applications

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  Digital Home
Digital Home

Best-in-class code density of ARC cores reduces memory size & power for digital home applications

more
 
Automotive/Industrial
Automotive/Industrial

Small, low-power ARC cores for automotive have high code density & the most DMIPS/mW in their class

more
  Storage
Storage

High-performance, low-power ARC processors support fast read/write speeds for SSDs and flash cards

more
   

The ARC Advantage: Maximum Performance With Minimum Area and Power

ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.

ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.

Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

The ARC Advantage: Implement Only the Hardware You Need to Optimize PPA

ARC processors are highly configurable, allowing designers to optimize the performance, power and area of each processor instance on their SoC by implementing only the hardware needed. The ARChitect wizard enables drag-and-drop configuration of the core, including options for
  • Instruction, program counter and loop counter widths
  • Register file size
  • Timers, reset and interrupts
  • Byte ordering
  • Memory type, size, partitioning, base address
  • Power management, clock gating
  • Ports and bus protocol
  • Multipliers, dividers and other hardware features
  • Licensable components such as a Memory Protection Unit (MPU), Floating Point Unit (FPU) and Real-Time Trace (RTT)
  • Adding/removing instructions

The ARC Advantage: Add User-Defined Instructions to Accelerate Code Execution and Lower Power Consumption

ARC Processor EXtension (APEX) technology enables ARC users to easily add their own custom hardware to the processor, dramatically boosting performance and/or reducing power consumption for their targeted application(s). ARC processors can be extended with:
  • User-defined instructions
  • User-supplied hardware (e.g., Verilog RTL)
  • Core registers
  • Auxiliary registers
  • Condition & status codes
  • Memory mapped blocks and closely coupled peripherals
ARC processor extensions enable users to dramatically improve performance, power and area. User-defined instructions, for example, can accelerate software execution, enabling the same code to run in much fewer cycles which reduces energy consumption by lowering clock frequency requirements (or enables the execution of more operations with the same energy.) Code size is also reduced, lowering memory requirements which leads to additional cost and power savings.



Power and cycle count reduction running sensor application software with APEX accelerators

The APEX interface also enables ARC users to tightly couple memory and peripherals to the processor, eliminating the need for additional bus infrastructure. The resulting "bus-less" design further reduces area and latency, increasing system-level performance while reducing costs.



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