RTL Synthesis & Test 

Accelerate Design Innovation with Design Compiler®   

Synopsys' Design Compiler family of products in the Galaxy Implementation Platform maximizes your productivity with its complete solution for RTL synthesis and test, Design Compiler Graphical, uses advanced optimizations and shared technology with IC Compiler place-and-route to deliver best in class quality of results for your most challenging designs at all process nodes. In addition, it enables RTL designers to predict, visualize and alleviate routing congestion and to perform floorplan exploration prior to physical implementation. Design Compiler Graphical also produces physical guidance to IC Compiler that tightens timing and area correlation and speeds-up placement runtimes. Design Compiler Graphical is built upon DC Ultra synthesis that concurrently optimizes for timing, area, power and test and includes topographical technology to reduce costly design iterations. And DC Explorer enables early RTL and floorplan exploration to accelerate development of high quality RTL and constraints leading to faster synthesis, and place-and-route.

The Design Compiler family also includes: the award-winning synthesis-based test solution for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon; Power Compiler, for low power synthesis and optimization; Formality for equivalence checking; and the DesignWare Library with its unequalled variety of synthesizable IP. This best-in-class, production-proven solution is integrated to achieve the industry's fastest and most predictable RTL-to-GDSII flow.

  • DC Explorer
  • Early RTL exploration to accelerate synthesis and place and routemore

  • DC Ultra
  • Concurrent Timing, Area, Power and Test Optimizationmore

Synopsys' synthesis-based test solution enables the most cost-effective path to high-quality manufacturing tests and high-volume silicon

Synopsys offers a broad portfolio of high-quality, silicon-proven digital, mixed-signal and verification IP for system-on-chip designs.

Key Benefits

Advanced Synthesis Technology that Accelerates the Entire Implementation Flow
  • Creates a better starting point for physical implementation and accelerates the entire flow
  • Early RTL exploration to speed development of high-quality RTL and constraints and accelerate design implementation
  • Synthesis results for timing, area and power correlated to within 5% of IC Compiler reduces design iterations
  • Physical guidance to IC Compiler to tighten correlation and speed placement by 1.5X
  • Push-button floorplan exploration for faster design convergence
  • Faster runtimes on quad-core compute servers
  • Congestion prediction to uncover routability issues before place-and-route
  • Physical visualization for early detection and debugging of layout issues
  • Seamless formal verification with Formality
  • Tight correlation with PrimeTime®, the industry's standard for timing sign-off

Best-in-Class Quality-of-Results for Area, Timing and Power
  • Most advanced timing, power and area optimizations
  • Specialized optimizations to reduce routing congestion
  • Concurrent multi-corner, multi-mode (MCMM) synthesis
  • Complete power management solution for low-power designs
  • Access to the industry's largest IP repository with DesignWare

Synthesis-Based Test and Design-Centric Yield Analysis
  • Fully integrated flow from DFT to ATPG, and from diagnostics to yield analysis
  • Shortens design cycle, increases productivity and provides highest timing and area correlation with physical results
  • Decreases manufacturing costs by significantly reducing both test application time and test data volume
  • High compression on pin-limited designs, down to a single scan channel
  • Power-aware testing to maintain high test quality and reduce yield loss on low power designs
  • Broad support for at-speed testing and advance fault models ensures ultra-high test quality
  • Implementation and verification of IEEE 1149.1 boundary scan design
  • Scalable embedded memory testing, repair and debug

NewsArticlesDatasheetsSuccess StoriesWhite PapersWebinarsVideos