Synopsys' Design Compiler® family in the Galaxy™ Implementation Platform maximizes your productivity with its complete solution for RTL synthesis and test, Design Compiler Graphical, uses advanced optimizations and shared technology with IC Compiler place-and-route to deliver best in class quality of results for your most challenging designs. In addition, it enables RTL designers to predict, visualize and alleviate routing congestion and to perform floorplan exploration prior to physical implementation. Design Compiler Graphical also produces physical guidance to IC Compiler that tightens timing and area correlation and speeds-up placement runtimes. Design Compiler Graphical is built upon DC Ultra™ synthesis that concurrently optimizes for timing, area, power and test and includes topographical technology to reduce costly design iterations.
DC Explorer, the newest addition to the Design Compiler Family, enables early RTL and floorplan exploration to accelerate synthesis and place-and-route. The Design Compiler family also includes: the award-winning synthesis-based test solution for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon; Power Compiler™, for low power synthesis and optimization; Formality® for equivalence checking; and the DesignWare® Library with its unequalled variety of synthesizable IP. This best-in-class, production-proven solution is integrated to achieve the industry's fastest and most predictable RTL-to-GDSII flow.