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DesignWare Controller IP for M-PCIe

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The DesignWare® Controller IP for M‑PCIe™ implements the port logic required to build a Root Port (RP), Endpoint (EP), Dual Mode (selectable RP/EP), or Switch device. The configurable and scalable DesignWare Controller IP for M‑PCIe is designed to the PCI Express® 3.0, 2.1, 1.1, M-PCIe ECN and Reference M-PHY Module Interface (RMMI) specifications. The high-quality, synthesizable IP is available in a variety of datapath widths, RMMI interface widths, and operating frequencies for optimizing size, power and throughput specifically to match the needs of an application. DesignWare Controller IP for M-PCIe integrates quickly and easily into system-on-chip (SoC) designs with a user-friendly application interface and timing suitable for a wide range of ASIC and FPGA technologies.

The DesignWare Controller IP for M-PCIe is based on the silicon-proven DesignWare Controller IP for PCI Express, which has been extensively validated with multiple hardware platforms, PHYs and PCIe® verification suites, reducing risk and improving time-to-market. Synopsys’ comprehensive PCI Express IP solution is in volume production and has been successfully implemented in a wide range of applications.

Register for the webinar: M-PCIe: Utilizing Low-Power PCI Express in Mobile Designs DesignWare IP for M-PCIe block diagram

Figure 1: DesignWare Controller IP for M-PCIe Block Diagram

DesignWare Controller IP for M-PCIe
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DesignWare MIPI M-PHY Datasheet

  • Comprehensive M-PCIe IP solution includes a suite of M-PCIe digital controllers and MIPI M-PHY IP
  • Support for all required features of the PCI Express Base Specification 3.0 in conjunction with the M-PCIe ECN
  • Support for all PCIe ports: Root Complex, Endpoint, Dual Mode, and Switch
  • Support for x1, x2, x4, x8, and x16 links
  • Support for M-PHY Gears 1, 2, and 3
  • Synopsys' optional selectable PHY technology allowing one controller instance to support both PCIe PHYs and M-PHY
  • RMMI interface for connection to Synopsys or third-party M-PHY IP
  • Optimized for low latency, low power, and low gate count
  • Application interface options include Native, AHB, AXI3, and AXI4
  • Optional embedded DMA controller
  • Implements full Transaction, Data Link, and Physical Layers including full configuration space register set(s)
  • Supports up to sixteen lanes at all three PCIe data rates and all three M-PHY gears
  • Available in 32-, 64-, 128-, or 256-bit datapath widths
  • Includes Synopsys selectable PHY technology allowing power-on PHY selection for PCIe or M-PCIe operation
    • PIPE PCI Express PHYs using 8-, 16-, or 32- bit interfaces, implementing “fixed data path” or “fixed clock” mode
    • RMMI M-PCIe PHYs using 10-, 20-, or 40 bit interfaces at Gears 1, 2, and 3 and Rates A or B
  • Optional bridges to AMBA AHB, AXI3, or AXI4 buses
  • Optional embedded DMA controller with up to 8 read and 8 write channels for high throughput with minimal SoC resource overhead
  • Supports up to 16 physical functions and up to 256 virtual functions using SR-IOV and ARI
  • Supports up to 8 virtual channels and up to 8 traffic classes
  • Supports the full range of PCIe-defined maximum packet sizes (128B to 4KB) and read request sizes (128B to 4KB)