The DesignWare Universal DDR controller family consists of three high-performance products, including the enhanced Universal DDR Memory Controller (uMCTL2), the Universal DDR Protocol Controller (uPCTL), and the Universal DDR Memory Controller (uMCTL), all of which support the JEDEC DDR2, DDR3, Mobile DDR, LPDDR2, and LPDDR3 SDRAMs standards.
The enhanced Universal DDR Memory Controller (uMCTL2) also includes support for DDR4 SDRAMs. The uMCTL2 delivers maximum bandwidth with minimum latency and provides designers with transparent access and complete control of the memory subsystem. This advanced multi-port memory controller accepts memory access requests from up to 16 application-side host ports. Application-side interfaces can be connected to the uMCTL2 either through standard AMBA (ACE-lite, AXI or AHB) bus interfaces for one or multiple ports, or via Synopsys’ custom-defined host-interface H-IF for single-port ultra low latency configurations.
The uMCTL2 offers two features to maximize bandwidth efficiency: high-priority bypass and configurable look-ahead. High-priority bypass allows designers to improve latency by bypassing the scheduling algorithm for more immediate access to the DRAM. The configurable, CAM-based, look-ahead feature provides intelligent scheduling to maximize throughput by prioritizing out-of-order transactions to the DRAM, allowing designers to make tradeoffs between area and performance.
The DesignWare Universal DDR Protocol Controller (uPCTL) serves the memory control needs of applications with simple transactions that do not require an internal scheduler. The streamlined command based low-latency native interface (NIF) also enables the uPCTL to be integrated with a custom application specific scheduler.
The Universal DDR Memory Controller (uMCTL) accepts memory access requests from up to 32 application-side host ports. Application-side interfaces can be connected to the uMCTL either through the standard AMBA AXI/AHB bus interfaces or via Synopsys custom-defined extended native interface (ENIF).
The uPCTL and uMCTL connect to the DDR PHY via a DFI 2.1 interface to create a complete memory interface and control solution. The uMCTL2 connects to the DDR PHY with a DFI 3.1 interface to support DDR4 and LPDDR3. The DFI3.1 interface is backward compatible and easily integrates with DDR PHYs that use a DFI 2.1 interface. The controllers also include software configuration registers, which are accessed through an AMBA 2.0 APB interface.
DesignWare Universal DDR Memory and Protocol Controllers Datasheet
Enhanced DesignWare Universal DDR Memory Controller Datasheet
- Match the single ported Universal DDR Protocol Controller with your own custom memory scheduler, or select a the complete multi-ported enhanced Universal DDR Memory Controller offering up to 16 host ports
- Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2 and LPDDR3 SDRAMs
- Compatible with all Synopsys DesignWare DDR PHYs (excluding DDR2/DDR PHYs)
- DFI 2.1 or DFI 3.1 compliant interface to DDR PHY (DFI 3.1 is backward compatible with DFI 2.1)
- Data rates up to 2400 Mbps in 1:2 frequency ratio, using a 600 MHz controller clock and 1200 MHz memory clock
- Data rates up to 1200 Mbps in 1:1 frequency ratio, using a 600 MHz controller clock and 600 MHz memory clock
|DDR Universal Memory Controller supporting DDR2, DDR3, Mobile DDR, and LPDDR2||STARs||Subscribe|
|DDR Enhanced Universal Memory Controller supporting DDR2, DDR3, Mobile DDR, and LPDDR2||STARs||Subscribe|
|DDR Universal Protocol Controller supporting DDR2, DDR3, Mobile DDR, and LPDDR2||STARs||Subscribe|