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DesignWare Universal DDR Memory and Protocol Controllers

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The DesignWare Universal DDR controller family consists of three high-performance products, including the Enhanced Universal DDR Memory Controller (uMCTL2), the Universal DDR Protocol Controller (uPCTL), and the Universal DDR Memory Controller (uMCTL), all of which support the JEDEC DDR3, DDR2, Mobile DDR, LPDDR2, and LPDDR3 SDRAMs standards. The Enhanced Universal DDR Memory Controller (uMCTL2) also includes support for DDR4 SDRAMs.

The uPCTL serves the memory control needs of applications with simple transactions that do not require an internal scheduler, while the uMCTL accepts memory access requests from up to 32 application-side host ports. The uMCTL2 delivers maximum bandwidth with low latency and accepts memory access requests from between 1 and 16 application-side host ports.

All the Synopsys Universal controllers connect to PHYs via the industry-standard DFI interface, and all their registers may be accessed through industry-standard APB busses.

Read more on the Synopsys blog, "Committed to Memory" and the white paper, "Achieve 10X DRAM Bandwidth Improvement with a DDR Controller Read Reorder Buffer".

DesignWare Enhanced Universal DDR Memory Controller Datasheet
DesignWare Universal DDR Memory and Protocol Controllers Datasheet
 

  • Select a complete multi-ported enhanced Universal DDR Memory Controller offering up to 16 host ports, or join a third-party scheduler to a single-port Enhanced Universal Memory Controller or Universal Protocol Controller
  • Support for JEDEC standard DDR2, DDR3, DDR4, LPDDR/Mobile DDR, LPDDR2 and LPDDR3 SDRAMs
  • Compatible with all Synopsys DesignWare DDR PHYs (excluding DDR2/DDR PHYs)
  • DFI 2.1 or DFI 3.1 compliant interface to DDR PHY (DFI 3.1 is backward compatible with DFI 2.1)
  • Data rates up to 3200 Mbps in 1:2 frequency ratio, using an 800 MHz controller clock and 1600 MHz memory clock (Dependent on process and PHY chosen)
  • Data rates up to 1600 Mbps in 1:1 frequency ratio, using an 800 MHz controller clock and 800 MHz memory clock (Dependent on process and PHY chosen)
DDR Universal Memory Controller (uMCTL) supporting DDR2, DDR3, Mobile DDR, LPDDR2, and LPDDR3STARsSubscribe
DDR Enhanced Memory Controller (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2STARsSubscribe
DDR Universal Protocol Controller (uPCTL) supporting DDR2, DDR3, Mobile DDR, LPDDR2, and LPDDR3STARsSubscribe

  Description DDR Enhanced Memory Controller (uMCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
  Name dwc_ddr_umctl2
  Version 2.40a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_ddr_umctl2
  Product Code 9220-0
  
  Description DDR Universal Memory Controller (uMCTL) supporting DDR2, DDR3, Mobile DDR, LPDDR2, and LPDDR3
  Name dwc_ddr_umctl
  Version 2.60a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_ddr_umctl
  Product Code 4721-0
  
  Description DDR Universal Protocol Controller (uPCTL) supporting DDR2, DDR3, Mobile DDR, LPDDR2, and LPDDR3
  Name dwc_ddr_upctl
  Version 2.60a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Cores
  Documentation
  Toolsets Qualified Toolsets
  Download dw_iip_DWC_ddr_upctl
  Product Code 3850-0