The DesignWare® ARC® EM Safety Enhancement Package (SEP) processor is designed for use in ISO 26262 safety-compliant automotive applications. The ARC EM SEP core combines a highly efficient and compact processor with integrated hardware safety features and a safety-certified compiler to enable automotive designers to achieve ASIL D (Automotive Safety Integrity Level D) compliance.
The EM SEP core is based on the ARC EM4 processor and the ARCv2 instruction set architecture (ISA) and delivers up to 1.76 DMIPS/MHz and 3.3 CoreMark*/MHz. When implemented on a 65-nanometer low power process technology, it can achieve up to 300 MHz with dynamic power consumption as low as 16 uW/MHz. Additionally, it offers a high degree of configurability, enabling designers to implement each core with the optimum combination of performance, silicon area, power consumption and code density for their specific application. The extensible ARC architecture allows integration of proprietary hardware accelerators which can further improve performance and power consumption.
The EM SEP core is supported by the DesignWare ARC MetaWare Compiler and accompanying safety documentation, helping developers of safety critical system to fulfill the requirements of the ISO 26262 standard. The compiler is part of the ARC MetaWare Development Toolkit, a complete solution for developing, debugging, and optimizing embedded software targeted for ARC processors. The safety collateral, including a safety manual and safety guide, simplifies designers’ document preparation for ISO 26262 compliance testing.
DesignWare ARC EM Safety Enhancement Package (SEP) Processor Core
ARC EM SEP Block Diagram
|ARC EM SEP 32-bit processor core, ARC V2 ISA, for embedded automotive safety applications||STARs||Subscribe|