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DesignWare STAR Hierarchical System

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The DesignWare® STAR Hierarchical System is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic cores and interface IP. It significantly reduces test integration time by automatically creating a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, and increases test quality of results (QoR), including optimizing test time and power through flexible test scheduling of IP and cores. It simplifies SoC test pattern creation by using the IEEE 1500 network to port IP or core-level patterns to the SoC-level, and allows silicon debug and diagnostics by enabling the IP debug test modes from the SoC level. The STAR Hierarchical System is compliant with the proposed IEEE standard P1687, which allows re-use of embedded test instruments for system-level debug. The system’s highly automated design-for-test (DFT) implementation and hierarchical IP and core-level test enables engineering teams to cut their test integration time to a matter of days and bring their designs to market faster and with lower design and test costs.

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DesignWare STAR Hierarchical System

DesignWare STAR Hierarchical System Datasheet
 



DesignWare STAR Hierarchical System
The STAR Hierarchical System is a new automated hierarchical test solution that reduces test integration time and improves test QoR for SoCs.

Yervant Zorian
Fellow and Chief Architect, Solutions Group, Synopsys

  • Hierarchical test accelerates SoC testing
  • Automated test integration and validation of all IP/cores on SoC increases design and DFT productivity
  • Flexible IP/core test scheduling optimizes test time and power
  • Automated porting of IP/core patterns to SoC-level enables reuse of test patterns
  • Optimized hierarchical IEEE 1500 network reduces area and signal routes
  • Efficient on-chip e-fuse programming for IP calibration/trimming
  • ATE based and interactive access to IP debug test modes enables faster production ramp
STAR Hierarchical System Wrapper Compiler SyncSTARsSubscribe
STAR Hierarchical System Wrapped Core Compiler SyncSTARsSubscribe
STAR Hierarchical System Reference ManualsSTARsSubscribe
STAR Hierarchical System Virtual Interface CompilerSTARsSubscribe
STAR Memory System Server CompilerSTARsSubscribe

  Description STAR Hierarchical System Reference Manuals
  Name dwc_shs_vl00x000vpnnstref000s
  Version a03
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare STAR Memory System
  Documentation Contact Us for More Information
  Download v-shs_vl00x000vpnnstref000s
  Product Code 7402-0
  
  Description STAR Hierarchical System Virtual Interface Compiler
  Name dwc_shs_vlxnx000vpnnstvic000s
  Version a08
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare STAR Memory System
  Documentation Contact Us for More Information
  Download v-comp_vlxnx000vpnnstvic000s
  Product Code 7402-0
  
  Description STAR Hierarchical System Wrapped Core Compiler Sync
  Name dwc_shs_vl00x000vpnnstawc000s
  Version a04
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare STAR Memory System
  Documentation Contact Us for More Information
  Download v-shs_vl00x000vpnnstawc000s
  Product Code 7402-0
  
  Description STAR Hierarchical System Wrapper Compiler Sync
  Name dwc_shs_vl00x000vpnnsmawr000s
  Version b08
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare STAR Memory System
  Documentation Contact Us for More Information
  Download v-comp_vl00x000vpnnsmawr000s
  Product Code 7402-0
  
  Description STAR Memory System Server Compiler
  Name dwc_sms_vl00x000vpnnstsrv000s
  Version a11
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare STAR Memory System
  Documentation
  Video
  Download v-sms_vl00x000vpnnstsrv000s
  Product Code 3842-0