EDA
System
IP
SolvNetPlus
Training & Education
Extended product information and access for existing Synopsys customers below.
Please visit the Synopsys IP SHS page for more information.
Highlights & Key Features
- Hierarchical test accelerates SoC testing
- Automated test integration and validation of all IP/cores on SoC increases design and DFT productivity
- Flexible IP/core test scheduling optimizes test time and power
- Automated porting of IP/core patterns to SoC-level enables reuse of test patterns
- Optimized hierarchical IEEE 1500 network reduces area and signal routes
- Efficient on-chip e-fuse programming for IP calibration/trimming
- Certified to support the ISO 26262 ASIL D standard for automotive functional safety
Product Details
Find Your IP
Search for IP
Quickly identify and access the right IP solutions for your project needs.
Foundation IP Selector
Find embedded memory and logic IP for your SoC design.
Non-Volatile Memory IP Selector
Find silicon-proven NVM IP for your SoC design needs.
Ask Synopsys
i
NOTICE: You are interacting with an AI-powered chatbot that provides general information about Synopsys, including its products and services, which may be incorrect or incomplete. In the event of any conflict or discrepancy, the terms of your applicable agreements supersede any information provided by this chatbot. These chats may be accessed by Synopsys and its service providers to customize the experience and improve this tool, and your use of this chatbot is an agreement to that data processing activity.