HOME   IP   EMBEDDED MEMORIES AND LOGIC LIBRARIES   NVM   DESIGNWARE AEON MTP LP/ULP IP  
Language: 日本語 | 简中

DesignWare AEON MTP LP/ULP IP

Search Tools

Spotlight

Synopsys DesignWare® AEON® Non-Volatile Memory (NVM) Multiple-Time Programmable (MTP) Low-Power (LP) and Ultra Low-Power (ULP) IP are optimized for power- and area-sensitive wireless applications and RFID and near-field communication (NFC) tags used in everything from logistics tracking to security and authentication.

Developed in standard 180-nm/3.3V process nodes, the MTP NVM IP offers best-in-class power consumption and enables MTP functionality required by the Gen2 EPC and ISO15693 RFID standards. Delivered as a hard IP block, the DesignWare AEON MTP LP/ULP NVM IP operates from a single 1.8V supply and includes support and control circuitry, including the high voltage generation and distribution required for programming.

Synopsys' new MTP ULP NVM IP offers a 50% area reduction over existing DesignWare MTP NVM IP, reducing system costs by using existing analog blocks already in the system. With single-bit read operation down to 0.9V, the IP reduces power consumption by up to 90% over the previous solution while supporting for up to 100,000 programming cycles, allowing for extensive reuse of RFID and NFC tags.

LP ULP
TSMC 180G SMIC 180LL SilTerra 180G TSMC 180G SilTerra 180G
Bit counts (bits) 64 -› 1k 64 -› 1k 64 -› 1k 128 -› 1k 128 -› 1k
Temperature range (ºC) -40 -› 85C -40 -› 85C -40 -› 85C -40 -› 85C -40 -› 85C
Endurance (write cycles) 10,000 10,000 10,000 100,000 100,000
Programming voltage (V) 1.6 -› 2.0 1.6 -› 2.0 1.6 -› 2.0 1.4 -› 2.0 1.4 -› 2.0
Read voltage (V) 0.9 -› 2.0 0.9 -› 2.0 0.9 -› 2.0 0.9 -› 2.0 0.9 -› 2.0
DesignWare AEON ULP MTP NVM IP Block Diagram
Figure 1: Block diagram of new DesignWare AEON ULP MTP NVM IP

DesignWare AEON MTP LP NVM for 180-nm/3.3 V Processes
DesignWare AEON MTP ULP NVM for 180-nm/3.3 V Processes
 

  • MTP LP/ULP IP
    • Multi-foundry support
    • Read operation down to 0.9V
    • >10,000 write cycle endurance
  • New MTP ULP NVM IP
    • 50% area reduction over previous generation
    • 90% programming power reduction over previous generation
    • Increased endurance to 100,000 write cycles
AEON MTP ULP NVM SILTERRA 180 GSTARsSubscribe
AEON MTP LP NVM SILTERRA 180 GSTARsSubscribe
AEON MTP LP NVM SMIC 180 LLSTARsSubscribe
AEON MTP ULP NVM TSMC 180 GSTARsSubscribe
AEON MTP LP NVM TSMC 180 GSTARsSubscribe

  Description AEON MTP LP NVM SILTERRA 180 G
  Name dwc_nvm_sl18ug7ssn16aemrdxxxi
  Version 3.02a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Embedded Memory IP
  Documentation
  Download dwc_nvm_sl18ug7ssn16aemrdxxxi
  Product Code 8192-0
  
  Description AEON MTP LP NVM SMIC 180 LL
  Name dwc_nvm_sm18uc7ssn16aemrdxxxi
  Version 3.00b
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Embedded Memory IP
  Documentation
  Download dwc_nvm_sm18uc7ssn16aemrdxxxi
  Product Code 8910-0
  
  Description AEON MTP LP NVM TSMC 180 G
  Name dwc_nvm_ts18ug7ssn16aemrdxxxi
  Version 2.01a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Embedded Memory IP
  Documentation
  Download dwc_nvm_ts18ug7ssn16aemrdxxxi
  Product Code 8892-0
  
  Description AEON MTP ULP NVM SILTERRA 180 G
  Name dwc_nvm_sl18ug7ssn16aemrd2
  Version 1.00a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Embedded Memory IP
  Documentation
  Download dwc_nvm_sl18ug7ssn16aemrd2
  Product Code A359-0
  
  Description AEON MTP ULP NVM TSMC 180 G
  Name dwc_nvm_ts18ug7ssn16aemrd2
  Version 2.02a
  STARs Open and/or Closed STARs
  myDesignWare Subscribe for Notifications
  Product Type DesignWare Embedded Memory IP
  Documentation
  Download dwc_nvm_ts18ug7ssn16aemrd2
  Product Code 9159-0