Synopsys' DesignWare® MIPI M-PHY IP is compliant to the latest MIPI® Alliance M-PHY specification and supports a wide range of high-speed interfaces for mobile applications including JEDEC Universal Flash Storage (UFS), MIPI Low Latency Interface (LLI), USB SuperSpeed InterChip (SSIC), MIPI DigRF v4, Unipro, and future CSI-3 and DSI-2.
The DesignWare MIPI M-PHY IP supports High-Speed Gear1, Gear2 and Gear3 rates A/B along with Type-I and Type-II low speed capabilities. The M-PHY’s modular architecture allows implementation of a variety of transmitter and receiver lanes to meet a broad range of applications and all modes outlined in the protocol specification. A sophisticated clock recovery mechanism and power efficient clock circuitry are designed to guarantee the integrity of the clocks and signals required to meet strict timing requirements. The DesignWare MIPI M-PHY supports large and small amplitudes, slew rate control and dithering functionality for optimized electromagnetic interference (EMI) performance. DesignWare DigRF v4 Master Controller Datasheet DesignWare MIPI M-PHY Datasheet DesignWare MIPI UniPro Controller Datasheet DesignWare UFS Host Controller Datasheet
Synopsys Demonstrates the Industry's First Silicon-Proven MIPI M-PHY
This video demonstrates the fully characterized, silicon-proven capabilities of the DesignWare MIPI M-PHY IP solution, highlighting its silicon performance as well as its electrical characteristics, which exceed target specifications.
Celio Albuquerque R&D Manager for DesignWare MIPI M-PHY IP