Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
The Synopsys DesignWare® USB 1.1 Host Controller (OHCI) Synthesizable IP is USB IP Host core that ASIC/FPGA designers can use to implement a complete USB OHCI Host Controller. The Host runs at Full and Low Speeds and is compatible with USB 2.0 and the Open HCI 1.0 specifications. By utilizing Synopsys' production-proven USB IP, designers can significantly reduce development time and engineering risk, and bring their USB-based solutions to market faster.DesignWare USB 1.1 OHCI Host Controller Datasheet
Configurable root hub supporting up to 15 downstream ports
Configuration data stored in Port Configurable Block
Single 48-MHz input clock
Simple application interface facilitates bridging the host to other system bus such as PCI, and the integration of the controller with chipsets and microcontrollers
Integrated DPLL
Support for SMI interrupts
Approximately 25K gates with 2 ports
Test Environment includes USB compliance tests and Bus Functional Models
