Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
The Synopsys DesignWare® USB Hub (UH01) is a set of synthesizable building blocks that ASIC/ FPGA designers can use to implement a complete USB Hub. The UH01 device is fully compliant with the USB 1.1 specification. By utilizing Synopsys' production-proven UH01 product, designers can significantly reduce development time and engineering risk, and bring USB-based solutions to market faster. The RapidScript® utility enables designers to easily configure the device by setting the number of downstream ports. UH01 is available in Verilog, facilitating synthesis into any ASIC/FPGA technology.DesignWare USB 1.1 Hub Controller Datasheet