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Power Optimization Kits

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Power Optimization Kits (POKs) enable designers to minimize power consumption while sustaining optimal performance and are available for DesignWare® Logic Libraries at 65-nm and below. Through a set of specially designed cells, POKs enable designers to shut down parts of a design to save power, or to dynamically operate function blocks at multiple voltages to achieve optimal trade-offs between dynamic power consumption and performance in multiple operating modes.

SiWare Logic Libraries
POK Components

28HP-TSMC Datasheet
28HPM-TSMC Datasheet
DesignWare Duet Embedded Memories and Logic Libraries for TSMC 40G Datasheet
 

  • Power Down Inactive Blocks on Chip
    • Save system power by powering down unused functions
    • Power gates manage shutdown and power-up
  • State Retention During Power-Down
    • Save key system states for rapid power-up
    • Unique area-saving live latch flops and classic save-restore latch flops
  • Multiple Supply Voltages and Voltage Scaling
    • Optimize power/performance for minimum power
    • Level shifters manage voltage island transitions
    • Level shifters characterized for cross voltages
  • Reverse Bias Operation
    • Reduce leakage in active circuits
    • Process compensation of die-to-die process variation
  • Patented circuits and structures for power optimization
  • Power-gating for domain shutdown
    • Maximum power savings
    • Multiple drive strengths enable fast wake-up times
    • With and without enable for daisy chain or high fan-out structures
    • Well modeling of bulk pins for clean LVS flow
  • Level shifters for multiple voltage islands
    • Up, down, up/down shifters
    • Wide shifting range from low voltage, standard voltage to overdrive
  • Isolation cells to prevent unknown states from unpowered domains
  • Data retention flip-flops
    • Standard save-restore latch flops
    • Live latch flops avoid area penalty of save-restore latch flops
    • Always-on cells powered by retention supply rail
  • Pitch matched to High-Density, High-Speed and Ultra High-Density cells
  • Available in standard and high VTs
  • Biasing cells for leakage control
  • Support for industry-standard EDA power flows
    • UPF and CPF