The multi-channel DesignWare PHY IP for PCI Express 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ demands for higher bandwidth. The PHY provides a cost-effective and low-power solution that is designed to meet the needs of today’s PCIe designs while being extremely low in power and area.
Using leading-edge design, analysis, simulation, and measurement techniques, Synopsys delivers exceptional signal integrity and jitter performance that exceeds the PCI Express standard’s electrical specifications. The high-margin, robust PHY architecture tolerates process, voltage and temperature (PVT) manufacturing variations and is implemented with standard CMOS digital process technologies. The PHY is small in area and provides a low-power, cost-effective solution that is designed to support PCI-SIG PCIe 3.1, 2.1, and 1.1 standards and to meet the needs of applications with high-speed chip-to-chip, board-to-board, and backplane interfaces.
The PHY IP for PCI Express 3.1 reduces both product development cycles and the need for costly field support by employing internal test features. The multi-tap transmitter and receiver equalizers, along with the advanced built-in diagnostics and ATE test vectors, enable customers to control, monitor and test for signal integrity without the need for expensive test equipment. This provides on-chip visibility into actual link and channel performance to quickly improve signal integrity.
As the leading provider of PCI Express IP, Synopsys offers a complete PCI Express 3.1 IP solution, including digital controllers, PCIe 3.1 PHY, and verification IP from a single vendor. Accessing all the IP from one provider allows designers to lower the risk and cost of integrating the 8.0 Gbps PCI Express interface into their high performance SoC designs.
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DesignWare PHY IP for PCI Express 3.1 Datasheet
DesignWare IP for PCI Express Complete Solution Datasheet
- Compliant with the PCI Express 3.1 (8.0 GT/s), 2.1 (5.0 GT/s) and 1.1 (2.5 GT/s) specifications as well as the PHY interface for PCIe (PIPE) 3 and 4 (8-bit, 16-bit and 32-bit) specifications
- Supports a wide range of PCI Express lane aggregation up to 16-lanes and full bifurcation
- Includes robust backchannel initialization and power management including L1 sub-state
- Exceeds electrical specifications in areas of margin and receive sensitivity for a robust design
- Built-in self test (BIST) including 7-, 9-, 11-, 15-, 16-, 23-, and 31-bit pseudo random bit stream (PRBS) generation and checker
- Automatic Test Equipment (ATE) test vectors for complete, at-speed production testing
- Industry's leading, complete PCI Express 3.1 IP solution: digital controllers, PHY and verification IP
- Supports advanced 28-nm and 14/16-nm FinFET technologies and flip-chip packaging
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