The ultra-compact DesignWare® ARC® 601 configurable 32-bit microprocessor is a member of the widely used ARC 600 family and is ideal for embedded and deeply embedded applications that require extremely low power consumption without compromising performance. Designed for multi-processor and portable applications the ARC 601 extends battery life and reduces cost while offering the performance required for a broad range of embedded applications.
The ARC 601 features Close Coupled Memory for both Instruction (ICCM) and Data (DCCM) to accelerate processing and keep implementation size and power consumption to a minimum. The RISC microprocessor core is user-customizable and highly configurable, enabling designers to tailor the ARC 601 to meet their specific application needs. Customers can also add user-defined instructions to the core with the easy-to-use ARC Processor EXtension (APEX) wizard and their own RTL (no need to learn special languages). The processor is based on the ARCompact 16-/32-bit Instruction Set Architecture (ISA) that implements 16-bit encodings of frequently used 32-bit instructions to reduce code size by as much as 40%. The 16-bit instructions can be freely intermixed with the 32-bit instructions in the DesignWare ARC 601 processor core to increase throughput and simplify program flow.
The exceptionally small silicon area and low power consumption of the core enables developers to achieve 32-bit performance at the price point and power level of an 8-bit microcontroller. The core is only 0.019 mm2 in size in a 40-nm G process but runs at 892 MHz (1070 DMIPS) consuming just 5 µW / MHz, so it packs a lot of performance into a very small power and area budget.
The ARC 601 core is supported by a full suite of software and hardware development tools. The suite includes the acclaimed MetaWare Development Kit that generates highly efficient code ideal for deeply embedded applications, the ARC simulators including xCAM and nSIM, and the ARChitect configuration tool.
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Evaluate ARC 600 Now DesignWare ARC 601 Datasheet
- Developed for embedded and deeply embedded applications
- Harvard architecture with 5-stage, 32-bit pipeline
- 26 general purpose registers, extendible to 54
- Deterministic and real-time instruction execution
- Efficient ARCompact 16/32-bit instruction set
- User-configurable program counter width: 16, 20 and 24-bits
- 512 B - 512 KB Instruction Close Coupled Memory (ICCM)
- 512 B - 256 KB Data Close Coupled Memory (DCCM)
- AHB, AXI or BVCI peripheral bus interface
- Up to 32 user configurable interrupts
- Optional 16x16 and 32x32 multipliers
- Optional 32-bit barrel shifter
- Zero overhead loop counter
- Optional CRC, normalize, swap instructions
- Support for custom instruction extensions
- Supported by a full suite of development tools
- JTAG debug interface with multi-core debug support
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