The DesignWare® DDR Memory Interface IP is a family of complete system-level IP solutions for system-on-chips (SoCs) requiring an interface to one or more of the broad range of high-performance DDR4, DDR3, DDR2, LPDDR, LPDDR2, LPDDR3, and LPDDR4 SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power and enhanced signaling features, the complete DesignWare DDR Memory Interface IP solution includes a choice of scalable digital controllers, an integrated hard macro PHY delivering silicon-proven memory system performance of up to 3200 Mbps per bit, and verification IP.
There are seven Synopsys DesignWare DDR PHY IP cores to choose from, as detailed in PHY Details tab, below.
All of the DFI-compatible DDR PHYs are supported by Synopsys' unique DesignWare DDR PHY Compiler.
Synopsys' DesignWare Enhanced Universal DDR Memory and Protocol Controller IP features a DFI-compliant interface, low latency and low gate count while offering high bandwidth. Optional market-specific features like AMBA AXI/AXI4 Quality of Service (QoS) and Reliability, Availability and Serviceability (RAS) features allow you to match the area and capabilities of the controllers to your needs. Check out DesignWare DDR Explorer for efficient DDR memory subsystem optimization.
Synopsys is the #1 DDR IP provider for a reason: see why Synopsys is the Trusted DDR IP Partner
DDR Complete Solution Datasheet