DDRn Memory Interface IP

Overview

The DesignWare® DDR Memory Interface IP is a family of complete system-level IP solutions for system-on-chips (SoCs) requiring an interface to one or more of the broad range of high-performance DDR4, DDR3, DDR2, DDR, LPDDR, LPDDR2 and LPDDR3 SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power and enhanced signaling features, the complete DesignWare DDR Memory Interface IP solution includes a choice of scalable digital controllers, an integrated hard macro PHY delivering memory system performance of up to 2400 Mbps per bit and verification IP through our DesignWare Verification IP (VIP) Alliance program.

There are six Synopsys DesignWare DDR PHY IP cores to choose from, as detailed in PHY Details tab, below.

All of the DFI-compatible DDR PHYs are supported by Synopsys' unique DesignWare DDR PHY Compiler.

There are two types of DDR digital controller IP cores to choose from: Synopsys' DesignWare Universal DDR Memory Controller (including the Enhanced version) and Protocol Controller IP cores feature a DFI 2.1 or 3.1 compliant interface (DFI3.1 is backwards compatible with DFI 2.1), low latency and low gate count while offering flexibility of clock frequency ratios between PHY and controller to allow easier timing closure in slower processes and lower latency in faster technologies.

Products
PHY Details

Universal DDR Controllers
DDR memory and protocol controller IP with a DFI-compliant interface more

Low-latency, area efficient controllers supporting DDR2/DDR3/mDDR/LPDDR2
PDF

DOWNLOAD DATASHEET

Standard DDR Controllers
DDR Memory and Protocol Controller IP with a proprietary PHY interface more

	DDR2/3-Lite Protocol Controller	Single-port Protocol Controller for DDR2/3-Lite and DDR2/DDR PHY's

	DDR3/2 Protocol Controller	High- performance, single-port Protocol Controller for DDR3/2 PHYs DOWNLOAD DATASHEET

	DDR2/DDR Memory Controller	Multi-port, configurable Memory Controller for DDR2/DDR PHYs

	DDR2/3-Lite Memory Controller	Multi-port, configurable Memory Controller for DDR2/3-Lite PHYs

	DDR3/2 Memory Controller	High-performance, Multi-port, configurable Controller for DDR3/2 PHYs

DDR4 multiPHY
Supports DDR4/3/3L/3U up to 2400 Mbps and LPDDR3/2 up to 1600 Mbps more

Supports DDR4 up to 2400 Mbps, DDR3/3L/3U up to 2133 Mbps and LPDDR3/2 up to 1600 Mbps
PDF

DOWNLOAD DATASHEET

Gen 2 DDR multiPHY
Support for LPDDR3/2 up to 1600 Mbps and DDR3/3L/3U up to 2133 Mbps more

Supports LPDDR3/2 up to 1600 Mbps and DDR3/3L/3U up to 2133 Mbps
PDF

DOWNLOAD DATASHEET

DDR multiPHY
Supports LPDDR2, Mobile DDR, DDR3/3L/3U and DDR2 in a single PHY more

Supports LPDDR2, LPDDR, DDR3/3L/3U, and DDR2 up to 1066 Mbps
PDF

DOWNLOAD DATASHEET

DDR3/2 SDRAM PHY
Supports speeds up to 2133 Mbps more

Supports DDR3/3L and DDR2 up to 2133 Mbps
PDF

DOWNLOAD DATASHEET

DDR2/3-Lite/mDDR SDRAM PHY
Mid-range performance PHY supporting speeds up to 1066 Mbps more

Area and feature-optimized IP solution operating at up to 1066 Mbps using Mobile DDR, DDR2 or DDR3 SDRAMs
PDF

DOWNLOAD DATASHEET

DDR2/DDR SDRAM PHY
DDR2 and DDR PHY supporting speeds up to 1066 Mbps more

Operates at speeds up to 1066 Mbps and is available in leading 130nm, 90nm and 65nm process technologies
PDF

DOWNLOAD DATASHEET

Synopsys offers six DesignWare DDR PHY IP cores supporting various SDRAM standards and data rates as outlined below:

DesignWare DDR PHY	SDRAMs Supported / Maximum Data Rate	Interface to Memory Controller	Typical Application
DDR2/DDR	DDR2 / 1066 Mbps DDR / 400 Mbps	Synopsys proprietary	Design in 130 - 65-nm that requires DDR2 support.
DDR2/3-Lite/mDDR	DDR3 / 1066 Mbps DDR2 / 1066 Mbps LPDDR / 400 Mbps	DFI 2.1	Design in 65 - 40-nm that requires DDR3 and/or DDR2 support up to 1066 Mbps along with LPDDR support.
DDR3/2	DDR3 / 2133 Mbps DDR2 / 1066 Mbps	DFI 2.1	Design in 65 - 28-nm that requires high performance DDR3 up to 2133 Mbps.
DDR multiPHY	DDR3 / 1066 Mbps DDR2 / 1066 Mbps LPDDR / 400 Mbps LPDDR2 / 1066 Mbps	DFI 2.1	Design in 65 - 28-nm that requires DDR3 and/or DDR2 support up to 1066 Mbps along with LPDDR/LPDDR2 support.
Gen 2 DDR multiPHY	DDR3 / 2133 Mbps LPDDR2 / 1066 Mbps LPDDR3 / 1600 Mbps	DFI 3.1	Design in 28-nm and below that requires high-performance mobile SDRAM support (LPDDR3) up to 1600 Mbps and/or high performance DDR3 support up to 2133 Mbps.
DDR4 multiPHY	DDR4 / 2400 Mbps DDR3 / 2133 Mbps LPDDR2 / 1066 Mbps LPDDR3 / 1600 Mbps	DFI 3.1	Design in 28-nm and below that requires high-performance DDR4/3 support up to 2400 Mbps and/or high performance mobile SDRAM support (LPDDR2/3) up to 1600 Mbps.