This edition of the DesignWare Technical Bulletin provides an overview and registration instructions for the
various IP tutorials that will be presented at the upcoming Synopsys Users Group (SNUG) in San Jose, CA, March 16-18.
Topics include DDR, USB 3.0, SATA and more. In addition, you will find the customary information on the latest whitepapers, webinars and "what's new" updates.
Constructing Timing Budgets and Improving Timing Margins for DDRn Memory Interface IP
Presenter: John Ellis, Senior Staff Research and Development Engineer
Tuesday, March 17th 10:30 a.m. to 12:00 p.m.
Each memory transaction requires that signaling must meet set up and hold requirements for a given frequency.
This tutorial will discuss the construction of timing budgets and the impact and significance of contributors from the transmitter, interconnect and receiver.
Typically, timing margins can be most readily improved by paying attention to the interconnect region.
Consequently, this tutorial will emphasize using good signal integrity practices to reduce interconnect related uncertainties such as crosstalk,
simultaneously switching outputs, impedance mismatch and inter-symbol interference.
Designing High-Speed Serial PHY IP for Chip-To-Chip, Storage and Backplane Applications
Presenter: Navraj Nandra, Director of Marketing, DesignWare Mixed-Signal IP
Tuesday, March 17th 1:30 to 3:00 p.m.
Increasing line speeds and port densities of communications and storage equipment require correspondingly faster board and backplane interconnect,
further increasing the design challenge of serial PHY's. Embedding high speed PHY IP into CMOS processes at 65 nm and 40 nm will present additional difficulties for designers.
This tutorial discusses designing the analog side of PHY IP for SATA, USB 3.0, PCIe 2.0 and 3.0 and the various physical effects caused by deep-submicron processes.
How to Address System-Level Issues in Your USB 3.0 Designs
Presenter: Terry Moore, CEO, MCCI Corporation
Tuesday, March 17th 4:00 to 4:45 p.m.
When designing high-performance and low power products, designers are faced with the challenge of identifying and resolving system-level issues early in the design process.
This tutorial discusses how MCCI, a system software provider, and Synopsys work together to develop test methodologies, tools and IP that help designers quickly validate USB 3.0 systems.
Achieve Higher Performance and Lower Power Consumption for Mass Storage Designs with SATA Device IP
Presenter: Bjorn Widerstrom, Corporate Applications Engineer
Wednesday, March 18th 10:15 to 11:45 a.m.
Serial ATA (SATA) is the mass storage interface of choice for hard disk drives,
optical disk drives and the newer NAND flash-based solid state drives, making the architecture and feature set of the SATA interface one of the most important aspects of the SoC design.
This tutorial will describe a set of easy-to-implement methods and best practices to help achieve performance goals, while maintaining low power consumption for the overall system
Getting 5 Gbps Performance Through 3 Meters of Cable With SuperSpeed USB IP
Presenter: Bob Lefferts, Director of R&D
Wednesday, March 18th 12:45 to 2:15 p.m.
USB 3.0 (Superspeed USB) delivers 10x the data transfer rate of USB 2.0, targeting next generation camcorders, portable media players, and smartphones.
USB 3.0 must operate at a fraction of the power-per-bit of USB 2.0, while transferring data at 5 Gbps with up to 3 meters of cable.
This tutorial examines the signal integrity issues and challenges when adding USB 3.0 into SoCs.
It will examine how equalizers, 8B10B coding, clock-data-recovery, and channel loss impacts USB 3.0 serial-links.
Managing System Bandwidth Requirements with a High Performance On-Chip Bus
Presenter: Fred Roberts, Corporate Applications Engineer
Wednesday, March 18th 3:15 to 4:45 p.m.
Faced with growing demands for higher system performance, it has become increasingly important to be able to effectively tune the bandwidth allocation for each master-slave link in the system.
This tutorial details an On-Chip-Bus architecture that enables the dynamic setting of bandwidth allocation at each arbitration point with reduced On-Chip-Bus area for predefined low performance links.
For more details on the full conference program visit the SNUG web site
IP Solutions for Synchronizing Signals that Cross Clock Domains
By Rick Kelly, R&D Manager
This paper explains the many types of synchronization issues that occur when clocks and data signals cross from one clock domain to another.
In all cases, the issues covered here involve clock domains that are asynchronous with respect to one another.
New Release of DesignWare OCP Verification IP
The new release of DesignWare OCP Verification IP includes various enhancements and quality improvements that have been done as a part of 1.40a and 1.50a FP releases.
New VMM-Enabled PCI Express System Example
The 6.50a release of the PCI Express Verification IP (VIP) provides a new VMM QuickStart code example for users just beginning verification projects who are unfamiliar with either the VIP, the PCI Express protocol, VMM, or SystemVerilog.
What's New in 2008.09 DesignWare Library Datapath and Building Block IP
The DesignWare Library introduced 6 new Building Block IP in 2008.09 release.
The DesignWare Library Datapath and Building Block IP are tightly integrated with Design Compiler® (DC) and are the part of the DC installation.
This release contains new Floating Point components, and combinational logic blocks.
All of these components are available in the DesignWare Library at no additional cost.
Now available on-demand:
- Virtualization of PCI Express I/O Devices
- Buying Time: Using Signal Integrity and Common Sense to Meet Timing Margins for High-Speed Memory Interfaces
- Decoding the Real Low Power Benefits of DDR for Embedded Applications
- Avoiding the Landmines When Using a DDR Interface on Your Next SoC