Synopsys Verification IP (VIP) provides verification engineers access to the industry's latest protocols, interfaces and memories required to verify their SoC designs. Deployed across thousands of projects, Synopsys VIP supports AMBA®, PCI Express, USB, MIPI, DDR, LPDDR, HDMI, Ethernet, SATA/SAS, Fibre Channel, OCP and other protocols as listed below.
Synopsys Verification IP (VIP)
Synopsys VIP solution is written in 100% native SystemVerilog to enable ease-of-use, ease-of integration and high performance. It supports advanced SystemVerilog-based testbenches with built-in methodology support for UVM and includes built in verification plans, coverage and checking to accelerate coverage closure. Verdi Protocol Analyzer is available to accelerate debug using a graphical protocol-aware environment.
Synopsys test suites are complete, self-contained and design-proven testbenches, written natively in 100% SystemVerilog UVM and targeted at protocol compliance testing. They are provided as source code enabling users to easily customize or extend the environments to include unique application-specific tests or corner-case scenarios.