Verification IP 

Overview 

Synopsys Verification IP (VIP) provides verification engineers access to the industry's latest protocols, interfaces and memories required to verify their SoC designs. Deployed across thousands of projects, Synopsys VIP supports AMBA, PCI Express, USB, MIPI, DDR, LPDDR, HDMI, Ethernet, SATA/SAS, Fibre Channel, OCP and others as listed below.

Synopsys Verification IP (VIP)

Synopsys VIP solution is written in 100% native SystemVerilog for best ease-of-use, integration and performance. It supports advanced SystemVerilog-based testbenches with built-in methodology support for UVM and VMM. Verdi Protocol Analyzer is available to accelerate debug using a graphical protocol-aware environment. Synopsys VIP solution includes many features to simplify testbench development, verification planning, coverage closure, error detection and improved simulation runtime.

Test Suites

Synopsys test suites are complete, self-contained and design-proven testbenches targeted at protocol compliance testing written natively in 100% SystemVerilog UVM. They are provided as source code enabling users to easily customize or extend their environments to include unique application-specific tests or corner-case scenarios.

  • Protocols
 
  • AMBA
  • Comprehensive support for AMBA 5 CHI, AMBA 4/3 AXI, ACE, AHB, APB & ATB 

AMBA 5 CHI
Verifies ARM® AMBA® 5 CHI



AMBA 4 AXI
Verify all complex interfaces in your AMBA AXI 4/3, ACE, and ACE Lite designs



AXI Interconnect Test Suites
Test Suite Overview in AMBA 4 AXI DS


  • Ethernet
  • Comprehensive support for Ethernet 10/100/10G/40G and 100G 

Ethernet
Verify all complex interfaces in your Ethernet 10/100/10G/40G and 100G, includes Test Suites



UNH Ethernet Test Suites
Source code test suites in plain text based on UNH compliance tests



  • HDMI
  • Verify all complex interfaces in your HDMI 2.0, 1.4b, 1.3 and HCDP 2.2 designmore

  • I2C
  • Verify all complex interfaces in your I2C designmore

  • I2S
  • Verify all complex interfaces in your I2S designmore


  • Memory
  • Comprehensive support for DDR and LPDDR memory VIP 

DDR4
Verify all complex memory interfaces in your DDR4 and 3 designs



DDR3
Verify all complex memory interfaces in your DDR3 design



LPDDR4
Verify all complex interfaces in your LPDDR4 designs



LPDDR3
Verify all complex memory interfaces in your LPDDR3 and 2 designs



LPDDR2
Verify all complex memory interfaces in your LPDDR2 design



UFS
Verify all complex interfaces in your UFS designs


  • MIPI
  • Comprehensive support for MIPI Titles 

CSI-2 (C-PHY, D-PHY)
Verify all complex interfaces in your MIPI CSI-2 design



CSI-2 Test Suites
Source code test suites in plain text to help with protocol compliance



DigRFv4
Verify all complex interfaces in your MIPI DigRFv4 design



DSI
Verify all complex interfaces in your MIPI DSI design



HSI
Verify all complex interfaces in your MIPI HSI design



M-PHY
Verify all complex interfaces in your MIPI M-PHY design



UniPro
Verify all complex interfaces in your MIPI UniPro designs


  • PCIe, M-PCIe and NVMe
  • Comprehensive support for PCIe Gen 4, 3, 2, 1, NVMe, and M-PCIe 

PCIe and M-PCIe (M-PHY)
Verify all complex interfaces in your PCIe Gen 4, 3 2, 1 and M-PCIe designs



PCIe Test Suites
Source code test suites in plain text to help with protocol compliance



NVMe
Verify all complex interfaces in your NVMe design


  • OCP
  • Verify all complex interfaces in your OCP 3.0, 2.0 designsmore

  • SAS
  • Verify all complex interfaces in your SAS designmore

  • SATA
  • Verify all complex interfaces in your SATA designmore

  • SDIO
  • Verify all complex interfaces in your SDIO designmore

  • UART
  • Verify all complex interfaces in your UART designmore

  • USB
  • Comprehensive support for USB 3.1, 3.0, 2.0 and Test Suites 

USB 3.0
Verify all complex interfaces in your USB 3.1, 3.0 and 2.0 designs



USB Test Suites
Source code test suites in plain text to help with protocol compliance



 
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