Synopsys Verification IP (VIP) provides verification engineers access to the industry's latest protocols, interfaces and memories required to verify their SoC designs. Deployed across thousands of projects, Synopsys VIP supports AMBA, PCI Express, USB, MIPI, DDR, LPDDR, HDMI, Ethernet, SATA/SAS, Fibre Channel, OCP and others as listed below.
Synopsys Verification IP (VIP)
Synopsys VIP solution is written in 100% native SystemVerilog for best ease-of-use, integration and performance. It supports advanced SystemVerilog-based testbenches with built-in methodology support for UVM and VMM.
Verdi Protocol Analyzer
is available to accelerate debug using a graphical protocol-aware environment. Synopsys VIP solution includes many features to simplify testbench development, verification planning, coverage closure, error detection and improved simulation runtime.
Synopsys test suites are complete, self-contained and design-proven testbenches targeted at protocol compliance testing written natively in 100% SystemVerilog UVM. They are provided as source code enabling users to easily customize or extend their environments to include unique application-specific tests or corner-case scenarios.