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SoC Architecture Analysis and Optimization for Performance and Power

Synopsys Platform Architect™ is a SystemC™ standards-based performance and power analysis tool for early SoC architecture exploration and design. Using transaction-level simulation , it reduces design time by predicting and optimizing architecture KPIs. ​

Platform Architect helps optimize hardware-software partitioning, IP selection and configuration, interconnect and memory configuration, and power. ​

Today’s SoC complexity means spreadsheet-based architecture tools are inefficient and run a high risk of re-spins to meet power and performance targets, resulting in higher costs and TTM delay.  With the largest library of architecture models, and fast capture of task and trace-based SW workloads, Platform Architect is the choice to shift-left your architecture design and deliver the right product on schedule.

In addition, Synopsys Platform Architect for Multi-Die Systems accounts for the interdependencies between multiple dies, or chiplets, within multi-die systems.

What's New

Key Benefits

Partitioning & Optimization
Partitioning & Optimization
Hardware-Software Partitioning and Optimization of Multicore Systems
Efficient Exploration
Efficient Exploration
Using Traffic Generation & Cycle-Accurate TLM Interconnect Models
Efficient Collaboration
Efficient Collaboration
Performance and Power for Root-Cause Analysis
Power Optimization
Power Optimization
SoC Interconnect and Memory Subsystem Performance and Power Optimization

Features

  • Extensive Model Library: Access the largest collection of transaction-level performance models for comprehensive system simulation.
  • Rapid Workload Capture: Quickly capture and analyze task and trace-based software workloads for efficient evaluation.
  • Application-Specific Support: Benefit from tailored support for AI, automotive, and networking applications to meet specialized needs.
  • Power Analysis: Perform system-level power analysis using IEEE-1801 UPF power monitors for accurate energy assessment.
  • Intuitive Tradeoff Analysis: Easily analyze tradeoffs and key performance indicators (KPIs) for optimal design decisions.
  • Design Space Exploration: Swiftly sweep through design spaces and conduct sensitivity analysis to identify optimal configurations.
  • User-Friendly Interface: Leverage an easy-to-use UI for dynamic modeling, simulation, and analysis of SoC architecture designs.
  • Automated Task Execution: Utilize a command line interface for automating architecture development tasks and workflows.
  • Standards-Based Simulation: Simulate environments using IEEE-1666 SystemC standards for consistency and reliability.
  • Collaborative Access: Enable role-based access with the Platform Architect Development Kit for team-based simulation and analysis.

 

potential schedule savings through early architecture exploration

What Our Customers Are Saying

Using Platform Architect™ MCO & Virtualizer™, we can build a virtual platform sooner, enabling architecture exploration, early software development and hardware performance verification at the highest level of the design phase for our SoC design.

Satoshi Aoki

|

Embedded Platform Development Department at Ricoh Company, Ltd.

Related Architecture Exploration Products

Resources

Video

Platform Architect Demonstration Running on ARC® NPX NPU Processor IP

Explore On-Demand Presentations from Our Annual Virtual Prototyping Day

Altera  A Stronger Performance Validation Continuum for Adaptive SoCs with Virtual Prototyping
Arteris  Enabling Informed Processor Core Selection through Early Architecture Analysis
Arteris  Performance Analysis for Network-on-Chip Development Using Synopsys Platform Architect
Bosch Using Verilator for Processor Benchmarking of Automotive SoC Platforms
Infineon Using Platform Architect for Architecting the Next Generation AURIX Microcontrollers
Intel Optimizing SoC Performance for Networking Workloads: Fabric, System Cache, and DRAM
Intel Multi-NoC SoC Performance Analysis and Architectural Exploration for Time Sensitive Networking (TSN) Applications
Kalray Interconnect and Memory Performance Exploration of Many-Core SoCs
Meta Enabling Informed Processor Core Selection through Early Architecture Analysis
Microsoft Pre-Design Verification and Optimization for On-chip Interconnects
ST NoC Design and Platform Integration for Early Benchmarking of Automotive Processor SoCs
Synopsys Benefits of Early Architecture Design for Multi-Die Systems