10:30 AM – 11:00 AM
Synopsys Design Platform with Fusion Technology for Arm-based designs
Erik Olson, Vice President of Applications Engineering, Design Group, Synopsys
Learn about the latest developments on the Synopsys Design Platform to improve PPA for Arm-based designs. Understand how the breakthrough Fusion Technology transforms the RTL-to-GDSII design flow with the fusion of best-in-class optimization and industry-golden signoff tools, enabling you to accelerate the delivery of your next-generation designs with the industry-best full-flow QoR and the fastest time-to-results. Customer examples and QuickStart Implementation Kits (QIKs) are also shared.
11:00 AM – 11:45 PM
Focus on Market Segment: Automotive, Mobile, Networking, Server, IoT
Listen to customer experiences and learn about their methodologies for achieving design goal metrics. Find out more about the end-market applications in automotive, mobile, server, networking, and IoT.
1:15 PM - 2:15 PM
Best Practices and QIKs for the Latest Armv8-A Processors
Jonah Chiu, Senior Applications Engineer, Design Group, Synopsys
JC Yu, Technical Marketing Manager, Physical Design Group, Arm
Learn from Synopsys tool experts the best practices and technologies to efficiently implement Arm's next-generation Armv8-A processors at 12/7nm to meet challenging performance targets, while minimizing dynamic and leakage power. Technology highlights include optimized implementation of compute-intensive modules to push performance while limiting IR drop, efficient leakage power optimization using multiple VT/channel width libraries, and optimized clock gating implementation.
2:15 PM - 3:00 PM
ANSYS: RedHawk Analysis Fusion Signoff-driven Flow within IC Compiler II
Benson Wei, Regional Technical Manager, Ansys
Understand how to achieve early, accelerated design optimization for power integrity and reliability with the RedHawk Analysis Fusion signoff-driven flow within IC Compiler II. Experience how the seamless integration enhances ease-of-use with virtually no learning curve, and enables up to 5X turnaround time improvement vs. point tool power integrity fixing flows.
3:15 PM - 4:00 PM
Latest Implementation Technology Update - Part 1
Dylan Hsu, Senior Applications Engineer, Design Group, Synopsys
Learn about the challenges posed for high-performance, energy efﬁcient implementation, and how IC Compiler II can help optimize PPA and accelerate time-to-market with its convergent flow that concurrently addresses congestion, timing, power, and area goals. Find more about advanced node requirements, and IC Compiler II's color-aware, multi patterning place-and-route flow. Finally, hear about the benefits of utilizing the in-design capabilities of IC Validator.
4:00 PM - 4:50 PM
Latest Implementation Technology Update - Part 2
Peter Tseng, Senior Applications Engineer, Design Group, Synopsys
Learn about advanced node synthesis challenges, and how Design Compiler Graphical can help achieve best-in-class quality-of-results with support for via ladders, layer aware optimization, pattern-must-join, inbound cell and pin access optimization. Realize high-performance, energy-efﬁcient signoff closure with PrimeTime (PBA-based ECO and power recovery, exhaustive PBA runtime gains), StarRC (simultaneous multi-corner and incremental extraction), and Custom Compiler co-design.