2017(第一届)ARC处理器北京峰会

您最前沿的嵌入式设计从这里开始

2017年11月15日

9:00 a.m. - 5:30 p.m.  

 

北京香格里拉饭店

中国北京紫竹院路29号

随着嵌入式系统变得越来越复杂,集成的功能也越来越高,SoC开发人员面临着开发更强大、更节能的设备的挑战。这些嵌入式应用程序中使用的处理器必须在有限的功率和芯片面积预算内高效地提供高性能的产品。

 

Synopsys ARC® 处理器峰会 是Synopsys主办的ARC处理器相关的技术和应用研讨会。会议报告由Synopsys专家、ARC用户以及ARC的生态系统合作伙伴主讲,内容覆盖全球电子市场的发展趋势以及基于ARC处理器特定的解决方案,应用于广泛的嵌入式领域,包括物联网、嵌入式视觉、移动、多媒体、汽车、存储等。

 

为了更好地服务中国用户,建立中国客户和美国专家以及合作伙伴沟通的桥梁,Synopsys 将在北京举办中国区的第一届ARC处理器峰会,邀请美国峰会的嘉宾出席,既糅合美国峰会的精华部分,也结合ARC进入中国多年的特色,并选择“中国集成电路设计业2017年会暨北京集成电路产业创新发展高峰论坛”(ICCAD) 前一天作为会议日期,为中国客户呈现原汁原味又具有中国特色的ARC处理器专业会议。这也是首次在北美以外的地区举办此类活动。

 

本次北京峰会邀请参会人员将涵盖人工智能、安全物联网、自动驾驶、存储、5G等领域的客户, 多达16个主题演讲。峰会在午餐和休息时间设有合作伙伴以及Synopsys 为您呈现的现场展示,内容丰富,精彩纷呈。峰会还给参会人员准备了精美的抽奖礼品。

 

本活动采取在线报名方式,即日起至11月10日请到点击此处进行注册报名

 

Synopsys诚挚邀请您参加2017第一届ARC® 处理器北京峰会。

 

联系人:Jojo Wang

Email:    jojowang@synopsys.com

手机:   13823126282

 

我们期待在初冬的北京见到您。

ARC处理器团队

 

ARC处理器北京峰会议程表 Agenda

时间

Time

议题

Topics

 

9:00am

Check-in

 

9:30am

Opening Remarks and Keynote: The Embedded Processor Revolution:

Solving High Performance Problems on a Low-Power Budget

Synopsys - Yankin Tanurhan,VP

(一楼大宴会厅III, Garden Wing Ballroom III / 1F)

 

10:30am

Break

 

 

AI/ EV / Automotive / Storage

(一楼大宴会厅III, Garden Wing Ballroom III / 1F)

Security / IoT

(二层莲花厅, Garden Wing Lotus Room / 2F)

 

10:45am

The Evolving Neural Network: Understanding and Applying the Latest CNN Techniques – Synopsys:  Gordon Cooper, PMM

Accelerating DSP Algorithms using ARC Processor EXtension (APEX) Technology in ARC EM9D/11D Processors – Synopsys:  Abhishek Bit, CAE

 

11:15am

Sound Processing in Smart Home Devices - A System Approach - Alango Technologies:  John Hu, GM of China

 

11:45pm

Progressive Pruning of CNNs to Reduce Memory Size and Bandwidth – MulticoreWare:  Lihua Zhang

Ultra-low power 3D micro-GPU for IoT class devices with DesignWare® ARC EM5D Processor - Think-Silicon: Iakovos Stamoulis, CTO &Co-founder

 

12:15pm

Lunch with "Birds of a Feather" Discussions and Demos

(一楼大宴会厅I及序厅  Garden Wing Ballroom I / 1F)

 

1:30pm

Play it Safe with the ARC EM Safety Island – Synopsys:  Fergus Casey, RD director

The Road to Processor Security – Smartchip:  Zhang HaiFeng, CTO

 

2:15pm

Eliminate Processor Bottlenecks with Tightly Integrated Processing Units for Embedded Vision – Synopsys:  Gordon Cooper, PMM

Using Power-Performance Efficiency ARC EM Processor to Differentiate Your IoT/AI Terminal Device - Gridchip & Synopsys:  Xiaofang Huo, CTO & Rick Wang, AE Manager

 

2:45pm

Machine Learning for Low-Power IoT Devices – Synopsys:  Jianying Peng, RD manager

IoT Demo Platform: Foundry, IP, Services - Brite Semi:  John Zhuang, CTO

 

3:15pm

Break

 

3:30pm

Next Generation PCIe Based Enterprise SSD solution using ARC processors -Starblaze:  Daniel Sun, Sr. Manager

No More Excuses: Secure Your SoC from IP Building Blocks to End-to-End Systems – Synopsys:  Fergus Casey, RD director

(3:30-4:15PM)

 

4:00pm

Low cost USB-SATA bridge architecture based on ARC - Sage Micro: Henry Hao, VP

 

Physical attacks on cyber-physical systems – OSR:  Junfeng Fan, Founder and CEO

(4:15-5:00pm)

 

4:30pm

Practical Considerations for Mapping a CNN Graph to an Embedded Vision Processor – Synopsys: Dexian Li, Senior AE

 

5:00PM

Lucky Draw

(一楼大宴会厅III,Garden Wing Ballroom III / 1F)

 

 

AI/ EV / Automotive / Storage Track

10:45-11:45am

The Evolving Neural Network: Understanding and Applying the Latest CNN Techniques

Synopsys: Gordon Cooper, Product Marketing Manager

The advances in computer vision research are continuing at a fast pace with rapid transitions from research topic to a implemented technology. This presentation will discuss the current and near future expectations for the evolving deep learning and embedded vision markets. Broader use cases for CNN will also be discussed -- like in radar and audio applications -- as well as other neural network techniques and applications involving RNNs.

 

11:45-12:15am

Progressive Pruning of CNNs to Reduce Memory Size and Bandwidth

MulticoreWare: Lihua Zhang

Research into CNN algorithms has evolved from finding the highest accuracy, to finding the highest accuracy with the least amount of computations. This presentation will discuss the latest techniques for graph pruning including a practical example and benchmark improvements.

 

1:30-2:15pm

Play it Safe with the ARC EM Safety Island

Synopsys: Fergus Casey, RD director

Developing ISO 26262 certified safety-critical automotive systems has created a new set of processing challenges for IC suppliers. This presentation will provide an overview of the key challenges to achieve ASIL D certification in a complex SoC and how ASIL D ready certified ARC EM Safety Island IP together with Synopsys STAR memory and logic test solutions can accelerate the development, verification, and certification process of automotive SoCs, reducing the overall safety investment within your SoC.

 

2:15-2:45pm

Eliminate Processor Bottlenecks with Tightly Integrated Processing Units for Embedded Vision

Synopsys:  Gordon Cooper, Product Marketing Manager

As embedded vision processing performance requirements increase and power and area goals remain aggressive, embedded engineers looking for the most optimized performance and power solution for vision are turning toward high-performance embedded vision processors tightly coupled with dedicated neural network engines. This presentation will describe how embedded vision processors, offering a combination of tight integration and scalability, can efficiently support high performance vision applications such as surveillance, autonomous driving and augmented reality.

 

2:45-3:15pm

Machine Learning for Low-Power IoT Devices

Synopsys: Jianying Peng, RD manager

Use of machine learning algorithms in IoT is proliferating dramatically. Multisensory context awareness, natural human to machine interfaces, and decision-making in various disciplines such as mechanical fault detection and personal healthcare are just a few examples of applications that would not be possible without these algorithms. The technology is migrating from traditional cloud-based services to local devices for better efficiency, autonomy and privacy. The multitude of artificial neural network classes and constantly increasing model complexity present a number of challenges for systems developers. This session presents approaches to solving the challenges of using machine learning technologies in low-power IoT devices.

 

3:30-4:00pm

Next Generation PCIe Based Enterprise SSD solution using ARC processors

Starblaze : Daniel Sun, Sr. Manager of Design Verification

High performance, small form factor and low power consumption are some key criterions in the design and selection of an SSD product. Enterprise SSD products are also characterized by a very high “mean time between failures” (MTBF) value, high data integrity and end-to-end data protection. Enterprise SSD products are expected to be used in heavy workload environments and still deliver high performance. This paper addresses some key challenges and requirements for the underlying CPU in an Enterprise SSD solution. It highlights how a multi-core ARC HS Processor and ARC EM Processor based SoC proves to be the ideal choice for the Enterprise SSD product, and explains how some key Enterprise SSD application requirements are easily met with ARC processors.

 

4:00-4:30pm

Low cost USB-SATA bridge architecture based on ARC

Sage Micro:  Henry Hao, VP

Portable storage products such as USB disks and mobile HDD/SSDs are sensitive to balance of cost and performance in consumer markets. For the target, it is all about a choice of embedded cpu and the chip architecture that leverages merits of a processor like ARC625D. This has been proven by the fact that USB2.0/3.0-to-Dual SATAIII bridge chip took ARC625D advantages of low power, configurability as well as compact in size, and turned out accepted by major brands such as Aigo, Apricorn and ThinkPad for mobile storage solutions.

 

4:30-5:00pm

Practical Considerations for Mapping a CNN Graph to an Embedded Vision Processor

Synopsys: : Dexian Li, Senior AE

In this presentation, you will learn the development flow and implementation considerations for moving from an academic CNN/deep learning graph to a commercial embedded vision design. The presentation will use practical examples that highlight the latest CNN graph mapping tool capabilities, including dispatched processing and pruning/compression. You will also learn about the cost vs. accuracy trade-offs of CNN bit width, balancing internal memory size and external memory bandwidth, and the importance of keeping data local to the CNN processor to improve bandwidth. Key deep CNN/learning benchmarks will be discussed including VGG16, Yolo, Denoiser, and more

 

Security / IoT Track

10:45-11:15am

Accelerating DSP Algorithms using ARC Processor EXtension (APEX) Technology in ARC EM9D/11D Processors

Synopsys: Abhishek Bit, CAE

Code efficiency and performance are critical requirements for modern digital signal processing systems. This session will present some key techniques and processor architecture features that can be used to accelerate typical digital signal processing algorithms. DSP examples and optimization strategies will be presented for the DesignWare ARC EM9D and EM11D Processors. ARC Processor EXtension (APEX) technology can accelerate such algorithms, significantly reducing memory footprint. The performance benefits obtained by using APEX can be further leveraged using the XY memory architecture on ARC EM9D and EM11D Processors.

 

11:15-11:45pm

Sound Processing in Smart Home Devices - A System Approach

Alango Technologies : John Hu, General Manager of China

Speech, as the most natural way we express ourselves, has tremendous potential as a method of human-machine interface. Speech recognition technologies have improved significantly but are still dependent on factors that influence the signal to “noise” ratio. During the last three years Alango, a leading provider of speech and audio enhancement DSP technologies, has accumulated significant practical experience in integration of front-end speech enhancement and speech recognition. In this presentation we will discuss all aspects of signal processing in Smart Home devices, including multi-microphone beamforming, echo cancellation, as well as keyword recognition and the computational resources necessary to perform such tasks. We’ll discuss both technology and system aspects. Additionally, we will share our vision for the voice interface of the future and discuss R&D topics to make it a reality.

 

11:45-12:15pm

Ultra-low power 3D micro-GPU for IoT class devices with DesignWare® ARC EM5D Processor

Think-Silicon : Iakovos Stamoulis, PhD, Chief Technology Officer, Co-founder

The emerging Internet-of-Things market, with display devices limited in area, performance, memory, thermal dissipation and battery capacity is adding design challenges for engineers.

The end-user is expecting the same fluid interaction and high–quality graphical-user-interface (GUI) experience known from their smart phones and tablets. Synopsys and Think Silicon developed a prototype sporting a DesignWare® ARC EM5D Processor with a NEMA®-GPU including NEMA® |GFX-API. The solution is aimed for developers to rapidly implement high-quality 3D graphics in connected ultra-low-power wearables and embedded devices with reduced risk and cost.

 

1:30-2:15pm

The Road to Processor Security

Smartchip: Haifeng Zhang, CTO

As the age of Internet of Everything is coming, the stability and the security requirements of the power supply are getting higher and higher. To enhance the safety and intelligent level of the power system, we will gradually build a suitable power grid security processor from the system level requirements to enhance the security of power equipment and power system.

 

2:15-2:45pm

Using Power-Performance Efficiency ARC EM Processor to Differentiate Your IoT/AI Terminal Device

GridChip & Synopsys: Xiaofang Huo, CTO & Rick Wang, AE Manger

Processing performance requirements for IoT/AI terminal devices continue to rise, however the battery life expected to be flat to down. This is causing Power-Performance efficiency to become the key for these applications. This presentation will describe some examples of improve the Power-Performance efficiency using ARC EM processor features and techniques, extending your IoT/AI terminal device’ life expectancy in the wild.

 

2:45-3:15pm

IoT Demo Platform: Foundry, IP, Services

Brite Semi : John Zhuang, CTO

The IoT market is filled with IoT platforms, many saving customers’ development time. Experience has proven that while reducing time to market is important, it is not the only thing required to build a successful platform. Brite Semi will discuss a new IoT Platform developed in a collaboration with SMIC and Synopsys that enables OEMs, system integrators, and startups to leverage a platform with innovative technologies from foundry, to IP & subsystems, and full spec to chip services.

 

3:30-4:15pm

No More Excuses: Secure Your SoC from IP Building Blocks to End-to-End Systems

Synopsys: Fergus Casey, RD director

 

Despite the cybersecurity media hype, security is still an afterthought in many designs. Instead of proactive, differentiating, future-proof security designs, security is generally considered a nuisance forced by regulations or an ad-hoc solution triggered by security breaches. Lack of knowledge, additional cost, and complexity are the typical excuses used. The resulting vulnerabilities range from simple software misconfiguration to more complex vulnerabilities such as side-channel leakage. To address these security challenges Synopsys offers a scalable range of security IP building blocks that offer the combined efficiency and security required for IoT applications. This presentation will describe how Synopsys reduces complexity and mitigates knowledge roadblocks by pre-integrating hardware and software IP into a Secure Subsystem that seamlessly fits into already standardized end-to-end security solutions like embedded SIM.

 

4:15-5:00pm

Physical attacks on cyber-physical systems

Open Security Research (OSR): Junfeng Fan, founder and CEO

While we all agree that IoT security is important, there is a general doubt about the threats of physical attacks on IoT devices. Both side-channel attacks and fault attacks require the hackers to obtain the victim device, therefore its threat seems to be limited. In this talk, we will give an introduction to physical attacks that could be applied to IoT devices, and show that some of them could scale. We also show how can IoT chips can be protected using advanced countermeasures.

 

Demos

DSP Pre-Processing in Voice Controlled Music Player -Alango

A demonstration of Alango’s Voice Enhancement Package (VEP).  VEP is a suite of real-time software DSP technologies designed for improving speech recognition performance in multi-microphone voice controlled multi-media devices.  The stereo music player demonstrated includes a 4 microphone array, Alango VEP pre-processing, and ASR software.  VEP functionality demonstrated include stereo acoustic echo cancellation and beamforming.

 

55-nm IoT Reference Platform - Brite Semi

This demonstration features a collaboration between Synopsys, Brite and SMIC that leverages Synopsys’ DesignWare ARC Data Fusion IP Subsystem and Brite’s test chip in SMIC’s 55-nm ultra-low-power process. Applications such as voice activation, gesture recognition, face detection and 9D sensor fusion are showcased. This ASIC platform significantly increases performance, lowers power consumption and reduces system cost for always-on IoT applications. 

Think Silicon NEMA® 3D GPU for IoT class devices with ARC EM5D Processor – Think Silicon

Synopsys and Think Silicon developed a prototype sporting a DesignWare® ARC EM5D Processor with a NEMA®- 3D GPU including NEMA®|GFX-API, 9D-Sensor, 5” TFT LCD and is fully battery powered. The solution is aimed for developers to rapidly implement high-quality 3D graphics in connected ultra-low-power wearables and embedded devices with reduced risk and cost.

 

Enterprise SSD Reference Design Platform - Starblaze

This demonstration shows Starblaze Technology SSD controller chip that leverages Synopsys’ ARC HS/EM CPUs and DesignWare portfolio IPs in TSMC’s 28-nm HPC process.

Real application scenarios, industry bench mark and features such as throughput, response latency, power consumption and volume capacity all showcased.

The 3D-TLC support, response latency, power consumption and features are competitive (Tier 1 group) in the real market.

 

Debug Tools for ARC---Ultra-XD real-time trace system and Opella-XD JTAG probe - Ashling

Ultra-XD trace probe allows capture and viewing of program-flow and data-accesses in real-time, non-intrusively for ARC HS or EM based applications. Captured trace can be turned into a “replay” file enabling you to debug your program by executing it both forwards and backwards within the MetaWare debugger. Opella-XD high speed probe, supporting all ARC cores, provides up to 3MB/s download speeds making it suitable for large, complex, software-intensive projects. The Opella-XD JTAG probe integrates with the MetaWare Development Toolkit or GNU GDB Debuggers under Windows and Linux based hosts.

 

ARC Embedded Products Display - SAGE

 

Complete Bluetooth Low Energy Link Layer and PHY IP -Synopsys

This demonstration features Synopsys’ complete DesignWare® Bluetooth Low Energy IP solution operating in two distinct roles – as a central device and a peripheral device. Synopsys’ Bluetooth Low Energy IP solution is compliant with Bluetooth 5 and Bluetooth mesh, and offers a compact, low-power wireless IP solution for IoT applications like wearables, smart home and smart city/industrial.

 

Real Time Object Detection with DesignWare EV6x Embedded Vision Processors - Synopsys

Security cameras and ADAS applications need to recognize objects in their surroundings. This live demo implements the TinyYOLO neural network on the EV6x Processor IP’s CNN engine to recognize and label items in the camera’s field of vision.

 

ARC processor competition in Chinese Universities and Synopsys ARC Wuhan Team introduction - Synopsys