VC VIP is implemented entirely in SystemVerilog and architected for native support of UVM and VMM without the need for methodology-level interoperability wrappers or language translations. It provides full visibility into classes, callbacks, and messages and enables true SystemVerilog-based constraints. This streamlining of the VIP structure results in much greater performance and methodology support; it also provides support across all simulators without degrading performance or methodology.
VC VIP includes productivity features to accelerate complex tasks like configuration and debug. It also provides features that address the need for protocol expertise and accelerate time to coverage-closure. It includes built-in test-plans, coverage,sequences and test suites.