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VC Verification IP for PCIe
Synopsys VC Verification IP (VIP) for PCI Express (PCIe) provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of PCI Express Gen1, Gen2, Gen3, Gen 4 and M-PCIe (M-PHY) designs.
Protocol Features
Application Layer
- Applications provides built-in scoreboarding via a shadow memory
- Driver application supports all transaction types
- Driver handles randomization, queuing, completions, and TLP checking
- Target application randomizes read completions and ordering
- Requestor application for automated testing of root and endpoint memory transactions
Information on Transaction Layer, Data Link Layer, PHY Layer can all be found in the datasheet.