VC Verification IP for PCIe

Synopsys VC Verification IP (VIP) for PCI Express (PCIe) provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of PCI Express 1.0, 2.0, 3.0, 4.0, 5.0, 6.0 and CCIX transport layer.

Read our blog on the latest PCIe 6.0 release here

Verification IP for PCIe

Highlights

  • Native System Verilog/UVM
  • Source code test suite (optional)
  • Runs on all major simulators
  • Built-in protocol checks
  • Verdi protocol-aware debug
  • Verification plan and coverage

Key Features

PCIe Test Suites Available

  • PCIe 6.0 (EA), 5.0, 4.0, 3.0, 2.0, 1.0
  • CCIX (EA)
  • PIPE, PCS/PMA level, SerDes, and application interfaces
  • Single model supports both root complex and endpoint
  • Spread spectrum clocking
  • Built-in host and target memories
  • Full-link speed and width negotiation up to 32 lanes
  • Applications with built-in scoreboarding to accelerate test development
  • Configurable pattern generation for random, directed, or erroneous patterns
  • Automated error injection at all layers (injection, verification and recovery)