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VC Verification IP for PCIe
Synopsys VC Verification IP (VIP) for PCI Express (PCIe) provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification of PCI Express Gen 1, Gen 2, Gen 3, Gen 4 ,Gen 5 and CCIX designs.
Protocol Features
- PCIe Gen 5 (Early Access)
- CCIX (Early Access)
- PCIe Gen 1, 2, 3 and 4
- PIPE, PCS/PMA level, SERDES, and application interfaces
- Single model supports both root complex and endpoint
- Spread spectrum clocking
- Built-in host and target memories
- Full-link speed and width negotiation up to 32 lanes
- Applications with built-in scoreboarding to accelerate test development
- Configurable pattern generation for random, directed, or erroneous patterns
- Automated error injection at all layers (injection, verification and recovery)