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PCI Express Test Suites
Writing tests to verify protocols is time consuming, challenging and requires deep protocol and methodology expertise. Synopsys testbenches help eliminate the task of writing compliance tests for today’s complex protocols.
The Test Suite for PCI Express (PCIe) is a complete self-contained, configurable environment targeted at the verification of PCIe 5.0, 4.0, 3.0, 2.0, and 1.0 designs. It is provided as SystemVerilog UVM source code to simplify integration, enable user customization and maximize reuse across projects.
Test Suite Features
- Support for PCIe 5.0, 4.0, 3.0, 2.0, and 1.0 speeds
- Dedicated retimer verification tests
- Provided as source code SystemVerilog UVM
- Configurable to act as Endpoint, Root Complex, PIPE SerDes, Serial
- PHY n-furation multiplexing support
- Provided framework for DUT application BFM
- Test plan to track pass/fail status referenced to PCI Express specifications
- Built-in coverage mapped to test plan
- Built-in data integrity checks
Sample Test Categories
- Gen 5 equalization
- Precoding
- Loopback
- ELBC
- Retimer
- TLP transaction
- ECRC
- Cpl timeout
- Ordering
- TC_VC
- TLP error message
- Atomic Operations
- DLLP transaction
- Flow control
- ACK/NAK
- LTSSM
- Enumeration
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