PCI Express Test Suites

Overview

Writing tests to verify protocols is time consuming, challenging and requires deep protocol and methodology expertise. Synopsys testbenches help eliminate the task of writing compliance tests for today’s complex protocols.

The Test Suite for PCI Express is a complete self-contained, configurable environment targeted at the verification of PCI Express Gen1, Gen2, Gen3 designs. It is provided as SystemVerilog UVM source code to simplify integration, enable user customization and maximize reuse across projects.

Test Suite Features

Support for PCI Express Gen1, Gen2, Gen3 speeds

Provided as source code SystemVerilog UVM

Configurable to act as Endpoint, Root Complex, PIPE, SERDES

Test plan to track pass/fail status referenced to PCI Express specifications

Built-in coverage mapped to test plan

Built-in data integrity checks

 

Sample test categories:

 

  • TLP transcaction
  • ECRC
  • Cpl timeout
  • Ordering
  • TC_VC
  • TLP error message
  • Atomic Operations
  • DLLP transaction
  • Flow control
  • ACK/NAK
  • LTSSM
  • Equalization
  • Enumeration