VC Verification IP for LPDDR3

Synopsys® VC VerificationIP for the JEDEC LPDDR3 memory protocol specification provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence on LPDDR3 based designs. VC VIP LPDDR3 is integrated with VC Protocol Analyzer, a protocol-centric debug environment that gives users an easy to understand, view of memory operations along with a consolidated view of entire address space of Memory. VC VIP LPDDR3 is written entirely in SystemVerilog to run natively on any simulator. Testbench development is accelerated with the assistance of built-in verification plans, functional coverage and example tests.

LPDDR3 VC Verification IP

LPDDR3 SDRAM Protocol Features

  • JESD209-3B JEDEC LPDDR3 Standard
  • 4Gb to 16Gb densities and x16 and x32 wide SRAM devices
  • Write leveling and ZQ Calibration
  • Power Off Sequence, Self Refresh, Deep Power Down, Partial Array Self-Refresh