VC Verification IP for DFI

Synopsys® VC Verification IP for DFI provides a comprehensive set of protocol, methodology, verification, and productivity features, enabling users to achieve accelerated verification closure of DFI based designs.

Synopsys VC VIP, based on its next generation architecture and implemented in native System Verilog/UVM, runs natively on all major simulators. VIP can be integrated, configured and customized with minimal effort. Test bench development is accelerated with built-in verification plan and functional coverage.

DFI VC Verification IP

Protocol Features

  • DFI 4.0 spec
  • All Interface groups Control
  • Write data
  • Read data
  • Update
  • Status
  • Training
  • Error
  • Low power control
  • All frequency ratios: 1:1, 1:2, 1:4
  • DDR4/LPDDR4 supported with UDIMM/RDIMM/LRDIMM