Verification Day 2020

A Special Interest Group Virtual Event
October 8, 2020

Why Attend?

This virtual event provides an opportunity to stay informed about the latest innovations, techniques and methodologies in static, formal and low power verification. This single-day event will share experiences and insights from users solving tough verification challenges using Synopsys solutions.

This year’s event will have a special focus on technology trends and case studies from domain experts in clock domain crossing (CDC), reset domain crossing (RDC), formal verification and low power verification. Attendees will leave with practical information to accelerate bug hunting using static and formal techniques to accelerate verification closure. 

For more detailed information on each session, view the full agenda here.

Who Should Attend?

Keynote Panel Spotlight

Thursday, October 8th

9:00 a.m. - 9:30 a.m. PT

How Verification Technologies Have Evolved to Support Chip Complexity

With SoC/ASIC design size growing exponentially, engineering teams are facing significant challenges to verify their next-generation designs.  This keynote panel, supported by Synopsys experts, will explore some of the challenges and opportunities using static, formal and low power verification. The panelists will highlight verification efficiency trends and technology advancements that are enabling chip designers accelerate time-to-market and improve design quality. 

Joe Mallett

Sr. Staff Product Marketing Manager, Synopsys

Per Bjesse

Synopsys Scientist

Kaushik De

Synopsys Scientist

Sean O'Donohue

Principal Engineer, Synopsys


Thursday, October 8th

9:00 a.m. - 3:00 p.m. PT

Formal Verification Track

Over the last few years formal verification usage has expanded. More and more design and verification teams are deploying formal to complement or replace simulation-based verification flows. Formal verification has always been known to find complex corner case bugs, but it did not provide enough information on verification completeness. With the arrival of the latest technologies and methodologies, there are new metrics available to define formal verification completeness and achieve signoff using a step-by-step process.

Static Verification Track

Contemporary chip designs contain a wide variety of functional errors and other design issues that may affect the quality of the end product. These range from inefficient or risky coding practices in register transfer level (RTL) design descriptions to complex hardware-software interaction bugs that show up only when running production applications. The goal of functional verification is to find all problems as early in the development process as possible. The commonly cited “rule of ten” states that it is ten times as much cost and effort to find and fix a bug as one moves from block-level design to chip-level verification (pre-silicon) and then to the bring-up lab and production use in the field (post-silicon). Even within the design phase, it is best to find issues as early as possible.  With increased complexity and growing chip size, its essential for designers to build methodologies which can help them root cause huge numbers to few clusters and address these violations with a constraint based methodology instead of using waivers for sign-off.

Low Power Technology Track

Designing for low power and energy consumption optimization are key issues for SoC designers. The earlier low power techniques can be applied to the design, the bigger their effect on overall power consumption. By introducing power management earlier in the design flow, at the system-level, design teams can benefit in several areas. From hardware block IP performance to software development, test and integration, designers can take advantage of many techniques to reduce power.  Low Power Verification solution's voltage-aware checking, modeling and simulation technology provides the needed accuracy and verification coverage for all low power designs, including the most advanced mobile SoCs with fine-grained power management. Static analysis and UPF power intent checking - including power state transitions, power shutdown and multi-rail macros - enable designers to rapidly find and fix low power bugs.

Formal Verification

9:30 a.m. – 10:10 a.m. PT

Verification Avengers – How Formal Super Heroes Save the Day

Presenter: Sean Safarpour, Group Director of Application Engineering, Synopsys

10:10 a.m. – 10:50 a.m. PT

Formally Signing-off Floating Point Datapath

Presenter: Lijun Li, Lead Formal Verification Engineer, Intel

10:50 a.m. – 11:30 a.m. PT

From Apps to Signoff: Climbing the Formal Deployment Pyramid

Presenter: Ipshita Tripathi, Formal Verification Lead, Qualcomm


Fastest Functional Coverage Development and Closure with Formal

Presenter: Luv Sampat, Engineer, Qualcomm & Matt Cummings, Sr. Staff Engineer, Qualcomm

11:40 a.m. – 12:10 a.m. PT

Ingredients for Creating A Success Story in RTL to RTL Equivalence Verification

Presenter: Arun Singh, Formal Verification Engineer, Samsung Austin Research Center (SARC)

12:10 p.m. – 12:40 p.m. PT

Eliminating Block Level Simulations with Full Formal Signoff

Presenter: Iain Singleton, Staff Applications Engineer, Synopsys & Paul Stravers, Principal R&D Engineer, Synopsys

Static Verification

9:30 a.m. – 10:10 a.m. PT

CDC/RDC Strategy and Signoff Methodology

Presenter: Alberto Carbajo, IC Digital Design Engineer, Analog Devices, Inc.

10:10 a.m. – 10:50 a.m. PT

Constraints Driven Clock Domain Crossing Signoff

Presenter: Ivan Svestka, Digital Design Engineer, Facebook

10:50 a.m. – 11:30 a.m. PT

Asynchronous Reset Logic Verification

Presenter: Mark Kelley, Sr. Staff Engineer, Xilinx

11:40 a.m. – 12:10 p.m. PT

Enabling Customer Success Through Robust CDC Methodology

Presenter: Luis Laranjeira, Director, R&D, Synopsys

12:10 p.m. – 12:40 p.m. PT

Advanced Technologies in Static Verification

Presenter: Rajarshi Mukherjee, Group Director, R&D, Synopsys

Low Power Technology

9:30 a.m. – 10:10 a.m. PT

Low Power Static Checking - New Challenges and Solutions

Presenter: Sayandeep Nag, Sr. Staff Engineer Manager, Qualcomm

10:10 a.m. – 10:50 a.m. PT

Power Model Framework with VCS, UPF, PrimePower and VCS NLP

Presenter: Anand Iyer, Principal Engineer, Microsoft

10:50 a.m. – 11:30 a.m. PT

Isolation Checks During a Pandemic

Presenter: Will Crocco, Corporate Chair for Multi-voltage Design Methodology, Intel

11:40 a.m. – 12:10 p.m. PT

Perform Multi-Voltage Checks Faster with Low Power Signoff

Presenter: Godwin Maben, Synopsys Scientist

12:10 p.m. – 12:40 p.m. PT

Achieving Successful Low Power Verification on A Tight Schedule

Presenter: Yuan Zong, Design Verification Engineer, Facebook


Agenda Details