VCS Xprop

Increasing the Efficiency of X-related Simulation and Debug

Verilog and VHDL are commonly used to model digital designs. Designers use RTL constructs to describe hardware behavior. However, certain RTL simulation semantics are insufficient to accurately model hardware behavior. Therefore, simulation results are either too optimistic or pessimistic as compared to actual hardware behavior.

Verilog and VHDL RTL simulators ignore the uncertainty of X-valued control signals and assign predictable output values because of these semantic limitations. As a result, RTL simulations often fail to detect design problems related to the lack of X-propagation. However, these same design problems can be detected in gate-level simulations, and often many gate-level simulations must be run only to debug X-related issues. With the new X-propagation support at RTL in VCS®, engineers can now save time and effort debugging differences in X-modeling between RTL and gate-level simulation results.

VCS Xprop

VCS® Xprop is designed to help find X-related issues at RTL and reduce the requirement for lengthy gate-level simulations. The simulation semantics of conditional constructs in both HDL languages, Verilog and VHDL, are insufficient to accurately model the ambiguity inherent in un-initialized registers and power on reset values. These issues are particularly problematic when the indeterminate states that are modeled as ‘X’ values become control expressions.

One of the most common sources of simulation differences highlighted when VCS Xprop is enabled is incorrect initialization sequences. The behavior is typically caused by a reset or clock signal transitioning from 0 to X, 1 to X or vice-versa. If a flip-flop is sensitive to the rising edge of its clock signal, an X to 1 transition will trigger the flip-flop and pass the value from input to output when coded using the Verilog posedge or the traditional VHDL flip-flop behavioral code: clk’event’ and clk’1’. Conversely, if the flip-flop is coded using the VHDL rising_edge(event) construct, the flip-flop will not load a new value. Effectively, the Verilog construct as well as one of VHDL constructs considers the X to 1 transition as true while the other VHDL construct considers it as false. However, in a VCS Xprop simulation, the same clock transition will cause the flip-flop to merge the input and output, possibly resulting in an unknown value. Hence, to effectively load new values onto a flip-flop, you must ensure that clock signals have valid and stable values, which will be shown in RTL run through a VCS Xprop enabled simulation.

VCS X-prop simulation and RTL simulation (Verilog semantics)