Increasing the Efficiency of X-related Simulation and Debug
Verilog and VHDL are commonly used to model digital designs. Designers use RTL constructs to describe hardware behaviors. However, certain RTL simulation semantics are insufficient to accurately model hardware behavior. Therefore, simulation results are either too optimistic or pessimistic as compared to actual hardware behavior.
Verilog and VHDL RTL simulators ignore the uncertainty of X-valued control signals and assign predictable output values because of these semantic limitations. As a result, RTL simulations often fail to detect design problems related to the lack of X-propagation. However, these same design problems can be detected in gate-level simulations, and often many gate-level simulations must be run only to debug X-related issues. With the new X-propagation support at RTL in VCS®, engineers can now save time and effort debugging differences in X-modeling between RTL and gate-level simulation results.
