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Faster Verification Closure from IP to SoC Using the Verification Continuum Platform | Synopsys

Synopsys
32K subscribers
1.7K views 4 years ago
This on-demand webinar explores how Synopsys’ end-to-end verification strategy scales from IP-level functional verification to full system-level validation and performance analysis using Synopsys verification engines and UFS verification IP. Learn more: https://www.synopsys.com/UFS-wp Learn more about Synopsys: https://www.synopsys.com/ Subscribe:    / synopsys   Follow Synopsys on Twitter:   / synopsys   Like Synopsys on Facebook:   / synopsys   Follow Synopsys on LinkedIn:   / synopsys   ...more
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Verification

Synopsys
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1

Building and Validating FreeRTOS-Based virtual ECUs with Synopsys Silver | Synopsys

Synopsys
2

Release Talk for TPT 2025.09 | Synopsys

Synopsys
3

Samsung Semiconductor India Research Uses Synopsys Tools | Synopsys

Synopsys
4

TPT 2025.09 | Synopsys

Synopsys
5

Requirements-Based Testing with TPT, Silver and Codebeamer | Synopsys

Synopsys
6

Zebu-200 & HAPS-200: Hardware-Assisted Verification Solutions for Emulation & Prototyping | Synopsys

Synopsys
7

Simulink Testing with TPT | Synopsys

Synopsys
8

TPT 2024.12 | Synopsys

Synopsys
9

RISC-V Design Innovations with Custom Extensions | Synopsys

Synopsys
10

DVCon 2022 Tutorial - 5 levels of RISC-V Processor Verification with ImperasDV | Synopsys

Synopsys
11

DVCon 2022: Synopsys and RISC-V Verification | Synopsys

Synopsys
12

Rebellions Discusses AI-chip Emulation using ZeBu | Synopsys

Synopsys
13

Synopsys Interview at embedded world 2024

RISC-V International
14

ImperasFPM Fast Processor Models - Jon Taylor, Synopsys

RISC-V International
15

Synopsys ARC-V™ Processor Family - Gordon Cooper, Synopsys

RISC-V International
16

HAPS high-performance RISC-V prototyping with asynchronous clocks | Synopsys

Synopsys
17

Synplify Synthesis Log File Tutorial | Synopsys

Synopsys
18

Synplify Project Flow Tutorial | Synopsys

Synopsys
19

A Scalable Approach to 2X Faster TAT for Arm Neoverse N2 Core Design Verification | Synopsys

Synopsys
20

Achieve 2X Performance When Verifying Multi-Die Systems in Synopsys VCS | Synopsys

Synopsys
21

Improve Your Software Team Productivity and Efficiency with Fast Virtual Prototypes | Synopsys

Synopsys
22

Faster Heterogeneous Integration with Synopsys Multi-Die System Solution | Synopsys

Synopsys
23

Learn About VC Formal Apps: Sequential Equivalence Checking (SEQ) | Synopsys

Synopsys
24

Learn About VC Formal Apps: Formal Register Verification (FRV) | Synopsys

Synopsys
25

Learn About VC Formal Apps: Automated Extracted Properties (AEP) | Synopsys

Synopsys
26

Discussing Formal Deployment, Architectural Verification, and Building a Formal Team | Synopsys

Synopsys
27

Multi Die Integration

Semiconductor Engineering
28

Lightelligence Accelerates the Architecture Design of their Next Generation Systems | Synopsys

Synopsys
29

Supporting & Growing Formal Verification Consulting Services | Synopsys

Synopsys
30

Leveraging Templates for Faster Code Development with Synopsys Euclide | Synopsys

Synopsys
31

Accelerating Validation of Next-Generation Cloud Architectures with Virtual Testing | Synopsys

Synopsys
32

Xiaolin Chen Speaks about Her Formal Journey | Synopsys

Synopsys
33

Leading Formal Innovations with Synopsys VC Formal 22.06 Release | Synopsys

Synopsys
34

HECTOR and VC Formal DPV, Past, Present, and Future | Synopsys

Synopsys
35

Extending the Saber Model Library with Analog Devices Components | Synopsys

Synopsys
36

Virtual Hardware “In-the-Loop” (vHIL) with the R-CAR Virtual Prototype and Simulink | Synopsys

Synopsys
37

Helicopters to Venus – Build and Debug Highly Reliable FPGA-based Designs | Synopsys

Synopsys
38

All You Need to Know about CXL Bring-up, Discovery and Traffic Exchange | Synopsys

Synopsys
39

Insight into the Analysis and Tracing capabilities of Virtualizer Studio - VDK Debug | Synopsys

Synopsys
40

Insight into the Embedded Software Debugger Flow using Virtualizer Studio - VDK Debug | Synopsys

Synopsys
41

Insight into the Virtualizer Studio – VDK Debug Perspective GUI | Synopsys

Synopsys
42

Accelerating Validation of Next-Generation Cloud Architectures with Virtual Testing | Synopsys

Synopsys
43

Addressing Exascale Emulation Debug Complexity – The Case for a System-Level Approach | Synopsys

Synopsys
44

Addressing the Challenges of Networking SoC Validation using Virtual Network Testers | Synopsys

Synopsys
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Faster Verification Closure from IP to SoC Using the Verification Continuum Platform | Synopsys

Synopsys
46

Faster Software Development using Hybrid Prototyping over PCIe Real World Interface | Synopsys

Synopsys
47

Synopsys Custom Design Family | Synopsys

Synopsys
48

Coding Testbench & RTL Using Synopsys Euclide | Synopsys

Synopsys
49

Better RTL and Testbench Code with Synopsys Euclide | Synopsys

Synopsys
50

Smart Everything: Powered by Silicon and Software | Synopsys

Synopsys
51

SaberRD Training 10: Model Characterization with the Power MOSFET Tool | Synopsys

Synopsys
52

Accelerate EV Electronic System Development with Virtual Prototyping | Synopsys

Synopsys
53

SaberRD Training 3: Operating Point and Small Signal Frequency Analysis | Synopsys

Synopsys
54

Software Development with Silver Virtual ECU | Synopsys

Synopsys
55

Synopsys VCS: Diving into the Warning SIOB (Select Index Out of Bounds) | Synopsys

Synopsys
56

Verification Challenges on the Cloud – The Data Storage Layer | Synopsys

Synopsys
57

Verification Challenges on the Cloud – The Compute Layer | Synopsys

Synopsys
58

IC Validator: Where to Find Documentation | Synopsys

Synopsys
59

IC Validator: Overview of the text_options() Function | Synopsys

Synopsys
60

IC Validator: Overview of the text_net() Function | Synopsys

Synopsys
61

IC Validator: Overview of the hierarchy_options() Function | Synopsys

Synopsys
62

IC Validator: Overview of the error_options() Function | Synopsys

Synopsys
63

IC Validator: Overview of the run_options() Function | Synopsys

Synopsys
64

Learn how to generate layout errors files from the PYDB Database | Synopsys

Synopsys
65

Learn how to generate an ASCII format error file from the PYDB database | Synopsys

Synopsys
66

Learn how to create and use waivers using PYDB | Synopsys

Synopsys
67

Learn how to create and use waivers using the VUE tool | Synopsys

Synopsys
68

Learn how to add host to a job already running | Synopsys

Synopsys
69

Learn how to run tool on multiple CPUs | Synopsys

Synopsys
70

Learn how to create a pattern library using the Pattern Library Manager | Synopsys

Synopsys
71

Learn how to perform Pattern matching in the tool | Synopsys

Synopsys
72

Learn how to create a pattern library | Synopsys

Synopsys
73

Learn how to run Signoff DRC in IC Compiler II tool | Synopsys

Synopsys
74

See how to debug results in IC Compiler II using the VUE tool | Synopsys

Synopsys
75

Learn how to load a replay file in VUE | Synopsys

Synopsys
76

Learn how to use the Connect Debugger utility from the VUE tool | Synopsys

Synopsys
77

Learn how to use the Error Heat Map to debug DRC errors | Synopsys

Synopsys
78

Learn how to connect VUE with IC WorkBench EV Plus, IC Compiler II | Synopsys

Synopsys
79

Learn how to fix GNFerror during LVS run | Synopsys

Synopsys
80

Learn about  output files available after an LVS run | Synopsys

Synopsys
81

Learn how to use the Short Finder function to debug text and compare shorts | Synopsys

Synopsys
82

Learn how to use the net trace utility to debug LVS results | Synopsys

Synopsys
83

Learn how Explorer detects design rules such as width, spnd iacing, anteracting checks | Synopsys

Synopsys
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Learn how to exit a job with partial results | Synopsys

Synopsys
85

Learn how to check runset syntax and generate a partially compiled runset | Synopsys

Synopsys
86

Learn how to execute a run-only job | Synopsys

Synopsys
87

Accelerating Wiring Design using Harness Architecture in SaberES Designer | Synopsys

Synopsys
88

Monitoring for Errors | Synopsys

Synopsys
89

Safe-Guarding I/O’s | Synopsys

Synopsys
90

Summary | Synopsys

Synopsys
91

Safe-Guarding FSM’s | Synopsys

Synopsys
92

Bug Elimination: Summary | Synopsys

Synopsys
93

Virtualizer Development Kits (VDKs) Demo – DesignWare MobileStorage | Synopsys

Synopsys
94

Protocol Aware Debug Using Verdi | Synopsys

Synopsys
95

Synopsys PowerReplay Solution - Introduction and Demo | Synopsys

Synopsys
96

Stay Ahead of the Automotive Curve with Virtual Hardware ECUs | Synopsys

Synopsys
97

Using HAPS FPGA-based Prototyping to Verify DesignWare USB Type-C IP Functionality

Synopsys
98

PCIe: Accelerating Verification | Synopsys

Synopsys
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Execution Profiling | Synopsys

Synopsys
100

Debugger Window Organization | Synopsys

Synopsys
101

Viewing Local and Global Variables and the Call Stack | Synopsys

Synopsys
102

Demonstration of the Synopsys Verification IP and Controller IP Core for PCIe 5.0 | Synopsys

Synopsys
103

Starting and Configuring the Debugger | Synopsys

Synopsys
104

Using Source and Disassembly Windows | Synopsys

Synopsys
105

Multicore Debugging | Synopsys

Synopsys
106

Using Breakpoints and Watchpoints | Synopsys

Synopsys
107

Casual is the New Formal – Formal Properties (Part 4) | Synopsys

Synopsys
108

Casual is the New Formal – Formal Constraints (Part 3) | Synopsys

Synopsys
109

HAPS-70 System for Debug Automation | Synopsys

Synopsys
110

Casual is the New Formal – Common Formal Results and Next Steps (Part 5)

Synopsys
111

How Good is Your Next Android SoC? Predict Performance and Power Using Task Graphs | Synopsys

Synopsys
112

Saber 2012.12 Release News | Synopsys

Synopsys
113

HAPS-DX | Synopsys

Synopsys
114

Accelerating Memory Debug | Synopsys

Synopsys
115

Safe-Guarding Memories | Synopsys

Synopsys
116

Driver Bring-up for DesignWare Multimedia (MMC) Host Controller using a Virtualizer Development Kit

Synopsys
117

Optimizing Your Mixed Signal Verification Environment Using CustomExplorer Ultra -- Part 2

Synopsys
118

Overcoming the Protocol Debug Challenge | Synopsys

Synopsys
119

Build an AMBA-based sub-system utilizing Synopsys solutions | Synopsys

Synopsys
120

Virtualizer Development Kits (VDK) USB Real- and Virtual- IO | Synopsys

Synopsys
121

Prototyping Imagination’s PowerVR Series 6XT dual-cluster 64-core GPU with HAPS | Synopsys

Synopsys
122

Casual is the New Formal – Formal Verification Design Setup (Part 2) | Synopsys

Synopsys
123

Addressing Complex SoCs with Advanced Verification Solutions | Synopsys

Synopsys
124

How To Integrate uvm_reg with AXI VIP | Synopsys

Synopsys
125

Prototype Timing Closure with Synopsys HAPS-80 | Synopsys

Synopsys
126

Speed IP Bring-up and SoC Validation with HAPS-DX | Synopsys

Synopsys
127

SaberRD Training 8: Modeling with Table Look-Up | Synopsys

Synopsys
128

Safe Unpacking and Packing of Synopsys HAPS Prototyping Systems | Synopsys

Synopsys
129

How and Where to “Design in” Functional Safety | Synopsys

Synopsys
130

Automotive Powernet Simulation & Fault Analysis Demo in SaberRD | Synopsys

Synopsys
131

Announcing ProtoCompiler for Multi-FPGA Prototyping | Synopsys

Synopsys
132

Functional Timing Accuracy with ESP Device Model | Synopsys

Synopsys
133

Casual is the New Formal - Introduction to Formal Verification and Planning (Part 1) | Synopsys

Synopsys
134

SaberRD Training 4: Test Automation | Synopsys

Synopsys
135

SaberRD Training 6: Introduction to Modeling | Synopsys

Synopsys
136

Debugging a USB 3 Linux Driver using Lauterbach TRACE32 and Synopsys VDK for ARM Cortex | Synopsys

Synopsys
137

Boost LED Driver Design for Automotive DRL Application Using SaberRD | Synopsys

Synopsys
138

Verifying and Debugging Storage Protocols: SATA | Synopsys

Synopsys
139

Introduction to ESP for Custom Design Formal Verification | Synopsys

Synopsys
140

Verdi OneSearch | Synopsys

Synopsys
141

Finding Root Cause of Unknowns in Batch | Synopsys

Synopsys
142

Cool Things You Can Do with Verdi – Verification Planning (Advanced)

Synopsys
143

Cool Things You Can Do with Verdi – Advanced Coverage Analysis Part I | Synopsys

Synopsys
144

SaberRD Training 1: Time Domain Analysis | Synopsys

Synopsys
145

Cool Things You Can Do with Verdi – Verification Planning (Introduction) | Synopsys

Synopsys
146

UPF Supply Sets Video Series – Part 1: Supply Set Handles | Synopsys

Synopsys
147

SaberRD Training 2: Schematic Capture and Parts Library | Synopsys

Synopsys
148

Automotive Powernet Modeling & Simulation using SaberRD | Synopsys

Synopsys
149

Cool Things You Can Do with Verdi – Advanced Coverage Analysis Part II | Synopsys

Synopsys
150

Advanced Interactive Debug with Verdi – Reverse Debug | Synopsys

Synopsys
151

AMS Co-simulation Debug with Verdi | Synopsys

Synopsys
152

Introduction to Saber: Power Conversion Demonstration | Synopsys

Synopsys
153

Cool Things You Can Do with Verdi - Introduction | Synopsys

Synopsys
154

Static Code Analysis: Scan All Your Code For Bugs | Synopsys

Synopsys
155

Unleashing SystemVerilog and UVM: Introduction | Synopsys

Synopsys
156

UVM-1: UVM Basics | Synopsys

Synopsys
157

SV-1: Object-oriented Programming for Designers | Synopsys

Synopsys
158

UVM-2: UVM Factory | Synopsys

Synopsys
159

Data Preparation for Verdi | Synopsys

Synopsys
160

FSDB Dumping | Synopsys

Synopsys
161

SV-2: The Power of Randomization | Synopsys

Synopsys
162

Interactive Debug with Verdi | Synopsys

Synopsys
163

SaberRD Quick Start Introduction (English) | Synopsys

Synopsys
164

Finding the Root Cause of a Wrong Value | Synopsys

Synopsys
165

Using nCompare to Compare Waveforms in Two FSDB Files | Synopsys

Synopsys
166

A Quick Tour of Verdi Coverage | Synopsys

Synopsys
167

Focus on Active Source Code with Verdi Source Code Viewer | Synopsys

Synopsys
168

Incrementally Trace in Schematic View | Synopsys

Synopsys
169

UVM-3: UVM Reporter | Synopsys

Synopsys
170

SV-3: The Power of Inheritance | Synopsys

Synopsys
171

Certainty in an Uncertain World: Building Functional Safety into FPGA Designs | Synopsys

Synopsys
172

Debugging Complex PCIe Issues using Synopsys VIP and Verdi Transaction Debug | Synopsys

Synopsys
173

The Evolution of Real Number Modeling | Synopsys

Synopsys
174

Synopsys PCIe Test Suites Demo | Synopsys

Synopsys
175

Advantages of Source-code SystemVerilog Protocol Compliance Test Suites | Synopsys

Synopsys
176

PCIe: Monitors and Test Suites | Synopsys

Synopsys
177

Why Synopsys selected a SystemVerilog VIP Architecture | Synopsys

Synopsys
178

Spec-based Coverage Closure with Synopsys VIP | Synopsys

Synopsys
179

Key Advantages of Synopsys Memory VIP Architecture | Synopsys

Synopsys
180

How to Integrate AXI VIP into a UVM Testbench | Synopsys

Synopsys
181

How to Use the AXI VIP Debug Port | Synopsys

Synopsys
182

Programming AXI-ACE VIP to Generate Error Scenarios | Synopsys

Synopsys
183

PCIe VIP: Accelerating Debug | Synopsys

Synopsys
184

Configuring Memory VIPs | Synopsys

Synopsys
185

Synopsys VIP Performance | Synopsys

Synopsys
186

Increase Productivity with Synopsys Memory VIP | Synopsys

Synopsys
187

Introducing Synopsys VIP for PCIe Gen4 | Synopsys

Synopsys
188

PCIe Gen4 - VIP/IP Solution with Protocol-Aware Debug and Source Code Test Suites | Synopsys

Synopsys
189

Demonstration of USB 3.0 SSIC Compliance Testing with MIPI M-PHY | Synopsys

Synopsys
190

Namespaces, Build Order, and Chickens | Synopsys

Synopsys
191

Customizing UVM Messages Without Getting a Sunburn | Synopsys

Synopsys
These chapters are auto-generated

Intro

0:00

Presenters

0:16

Protocol Verification Drivers

2:58

Cost and Time-to-Market Pressure

15:50

Synopsys Verification Continuum Platform

18:00

Addressing Protocol Verification Challenges

21:13

Synopsys Protocol Continuum Scaling from Simulation to Emulation Simulation Simulation Acceleration

28:50

UFS Device Verification Requirements Customer problem statement To develop UFS Device P for integration with the automotive Soc

31:13

UFS Device Verification Setup

32:32

Pure simulation Design under test (DUT)

33:50

UFS RTL on Pure-simulation Design under test (OUT) - UFS Application Layer RTL

36:23

Subsystem Acceleration Design under test (OUT) - Subsystem components Verification Components

38:14

Emulation Design under test (DUT) - UFS Subsystem (UFS Device + UniPro + M.PHY)

42:08

System validation and software development Design under test (DUT) - UFS Subsystem (UFS Device + UniPro + M.PHY)

44:37

Conclusion

47:58
Faster Verification Closure from IP to SoC Using the Verification Continuum Platform | Synopsys
9Likes
1,778Views
2021Jul 20
This on-demand webinar explores how Synopsys’ end-to-end verification strategy scales from IP-level functional verification to full system-level validation and performance analysis using Synopsys verification engines and UFS verification IP. Learn more: https://www.synopsys.com/UFS-wp Learn more about Synopsys: https://www.synopsys.com/ Subscribe:    / synopsys   Follow Synopsys on Twitter:   / synopsys   Like Synopsys on Facebook:   / synopsys   Follow Synopsys on LinkedIn:   / synopsys  

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Synopsys

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