Functional verification dominates semiconductor development, consuming the largest percentage of project time and resources. Verification is never truly complete, so the decision to release a chip for software development on an emulation or FPGA prototyping platform, or for physical tape out, is based on a combination of factors. Verification engineers want to see key metrics converge to target goals, and do so with stringent cost and time constraints. Innovation that can accelerate this convergence and help find bugs sooner deliver high value by “shifting left” the verification process and therefore tape out and software development. In Part 1 of this webinar series, we explored some of Synopsys’ innovative new features in simulation and debug that can uniquely improve verification efficiency and productivity.
In this Synopsys webinar, we will review Synopsys’ new Intelligent Coverage Optimization (ICO) technology, which reduces coverage regression turn-around time (TAT), while improving coverage and exposing rare bugs. ICO leverages AI/ML technologies to accumulate and learn from project experience, and deliver increasing optimization benefits over regression runs. ICO fits seamlessly in Synopsys VCS constrained random verification technologies and flows, and is an important new tool for verification engineers to use as part of Synopsys’ overall shift left solution.