Low power is an increasingly critical requirement for all modern SoCs. Moreover, it is becoming more and more difficult with complex architectures being used in modern designs. This has made it necessary for designers to invest heavily in this verification effort throughout the design development cycle starting from architecture definition, RTL development, to final netlist tape-out.
Conventionally, static low power flow constitutes defining and cleaning up of UPF power intent at the RTL stage, verifying the UPF power intent netlist stage, and finally performing consistency as well as integrity checks during final PG netlist signoff. The need to fit all these stringent requirements within tight project schedules dictates the crucial need to identify most UPF related design issues early at the RTL stage itself. Having a solution that considers low power structures that are not yet placed within the design at the RTL stage has been far-fetched until now. Predictive analysis of an early RTL design stage provides the most befitting solution to meet this time-critical task.
In this Synopsys webinar, you will learn how Synopsys’ VC LP enables users with early predictive analysis enabling achievement of significantly shorter design cycle by finding critical low power bugs at the RTL stage rather than at simulation or implementation. A plethora of low power checks including: electrical and functional impact of LP intent supply connectivity issues, functional issues, and architectural issues will also be covered. Further, you will find how predictive analysis technology can act as a key ingredient, allowing various other Synopsys solutions such as VC SpyGlass Lint, CDC, RDC, and VC Formal to become power-aware for exhaustive low power static verification in its entirety.