Synopsys Webinar

Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple asynchronous clock and reset domains. Ensuring all clocks propagate concurrently across each clock tree components used as clock switching elements or each sequential or combinatorial component, clock output of which becomes asynchronous with respect to the clock input while maintaining predictability of design functionality requires exhaustive CDC verification.

In addition to relying on a robust design specification, it becomes imperative to take advantage of a smart EDA tool that infers all critical design paths including all clocks, clock control signals, clock domain at IP’s boundary level and even the resets for CDC or RDC paths ultimately flagging any unpredictable design behavior. VC SpyGlass CDC and RDC completely meets these verification needs by back-tracing and reporting all signals that needs to be constrained for optimized coverage of the structural verification, eventually delivering high quality of results (QoR) for CDC and RDC analysis. 

Proceeding this way prevents the direct reuse of STA (Static Timing Analysis) constraints that may lead to an optimistic configuration, such as the propagation of synchronous clocks instead of asynchronous ones, or other mismatches between CDC analysis and STA, which would limit the number of the analyzed CDC paths.

In this web seminar, we will present the different steps required to manage the constraints generation and elaboration during CDC and RDC analysis. An efficient static low-power verification approach concerning low-power components defined through the UPF file directives will also be illustrated. Lastly, we will conclude by demonstrating ways to manage the different aspects of constraints using VC SpyGlass as an open tcl tool allowing the elaboration of additional and custom features increasing the QoR compared to the native platform.

Speakers

Listed below are the industry leaders scheduled to speak.

Jerome Avezou

Senior Staff Applications Engineer
Synopsys

Jerome Avezou is Senior Staff Application Engineer in the Customer Success Group at Synopsys. In his current role, he supports static verification products, manages various customer engagements and helps architect customer flows

During his 30 years of experience, he developed skills in the field of EDA tools, front-end design methodologies and scripting He holds Master’s Degree in Computer and Electronic Engineering, Efrei Villejuif/Paris.

Diana Kalel

CDC-RDC Verification Engineer
STMicroelectronics

Diana Kalel is a hardware verification engineer working on the CDC and RDC analysis at ST Microelectronics. She is currently pursuing a PhD specializing in different structural and functional verification flows of CDC and RDC verification. Academically, she holds a bachelor’s degree from the faculty of Engineering Ain Shams University, Cairo, Egypt and a master’s degree in Microelectronics and Digital Design from Grenoble Alpes University, Grenoble, France.

Jean-Christophe Brignone

CDC-RDC Verification SMTS
STMicroelectronics

Jean-Christophe is a Senior Member of Technical Staff (SMTS) in the field of CDC and RDC verification in the CPU division, STMicroelectronics, leading the company-wide reference flow working group. Previously, he has extensively led various front-end tasks namely RTL integration, verification, synthesis, formal proof, DFT and STA.

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