This webinar will showcase the design, analysis, and optimization of a multi-die fabric architecture based on the next generation Arm® CoreLink™ CMN-700 interconnect, a high-performance cache coherent interconnect solution designed for complex multi-die system-on-chip (SoC), such as those found in data centers. Attendees will learn how to use the Arm CMN-700 Performance Model in Synopsys Platform Architect™ to improve the overall architecture of the multi-die system.
A case study will illustrate how characteristic workload models can be used to analyze the performance of the architecture and identify potential bottlenecks. This webinar will provide attendees with valuable insights into removing these bottlenecks thereby providing high-bandwidth, low-latency movement of data between processor cores, IO and memory. Additional configuration, debug and visualization capabilities of Synopsys Platform Architect that enable these optimizations will be demonstrated.
Whether you are a chip architect or a system designer, this webinar will provide valuable insights on how to design and optimize your high-performance, multi-die chip architecture.