HSPICE SIG 2017

Design Verification for Robustness in Advanced Technologies

The 2017 HSPICE SIG presentations focus on challenges and solutions for FinFET circuit analysis and verification to ensure design robustness.

The Synopsys HSPICE special interest group (SIG) is an active community for all HSPICE users and design engineers who want to stay connected with the latest developments in the field of circuit simulation.

On February 2, 2017, Synopsys hosted an HSPCIE SIG event in Santa Clara, CA. At this event, several  industry leaders shared their experiences on transistor-, block-, and package-level design.

Speakers

Tony Todesco

HSPICE SIG Event Emcee

SMTS Design Engineer, Methodology and CAD Group, AMD

Jane Xi

HSPICE New Feature Enablement in Advanced Technologies

Sr. Staff Engineer, Xilinx

Tom Mahatdejkul

Tom Mahatdejkul

Principal Design Engineer, ARM

John Ellis

Simulating PSIJ Effects in Low BER DDR4 Interfaces using StatEye

Principal Engineer, Synopsys Mixed-Signal IP Group

Scott Wedge

Engineering in an Uncertain World—Predictability with HSPICE

Principal HSPICE R&D Engineer, Synopsys