DVCon India 2019

Visit Synopsys at Booth #4

Location: Radisson Blu Bengaluru

Exhibit Hours:
Wednesday, Sept. 25th: 11:00am - 6:30pm
Thursday, Sept 26th: 11:00am - 4:00pm

Conference Keynote

Wednesday, Sept. 25th 9:45am - 10:30am | Grand Victoria Ballroom

The Evolution of Static Verification

Synopsys Keynote at DVCon India 2019

This keynote looks at the static verification landscape and how it has evolved to support chip complexity, along with the unique challenges and opportunities posed by sophisticated chips for automotive systems, AR/VR platforms, and AI applications with 5G connectivity. Can machine learning help designers be productive and mitigate growing SoC challenges?

Synopsys Poster Presentations

  • Use of Message Bus Interface to Verify Lane Margining in PCIe
  • Verification Strategies and Modelling for the Uninvited Guest in the System: Clock Jitter
  • From Device Trees to Virtual Prototypes