DVCon China 2018

Visit Synopsys at Booth #5

Location: DoubleTree by Hilton Shanghai-Pudong

Exhibit Hours: Wednesday, April 18, 10:00am - 7:30pm


Conference Keynote

Wednesday, April 18, 9:00am - 9:30am | Ballroom AB

Industry’s Next Challenge: The Petacycle Challenge

Chris Tice, VP of Verification Continuum Solutions

This keynote highlights how new growth segments in the industry, such as Automotive, IoT, Networking, 5G Mobile, etc. are fundamentally changing the requirements for verification. The keynote will emphasize how addressing the SoC verification, software bring-up and validation needed for these segments will change the nature of verification technologies and solutions. 

DVCon China 2018

Synopsys Tutorial

Wednesday, April 18, 1:00pm - 2:30pm | Ballroom B

Synopsys FPGA Platform – Enabling Significant Productivity Gains in Design, Verification and Debug of FPGA-based Designs

The size and complexity of FPGA designs are getting larger with each design and designers are asked to achieve more with less. As the complexity grows, FPGA designers are under increasing pressure to accelerate designs, which has the potential cause more bug escapes. This means that FPGA designers need to segment the design flow into multiple phases to gain productivity improvements at each phase. This flow includes planning, static and formal verification, simulation synthesis and system debug, and FPGA designers need sophisticated solutions to help automate and accelerate the overall design flow with the goal of finding and fixing bugs faster with the highest performance in the smallest area.

This tutorial will detail how Synopsys solutions provide designers with industry leading tools along with native integrations, faster performance and technology advancements, to achieve the fastest time to market and highest quality FPGA designs.

Synopsys Booth #5

Synopsys delivers comprehensive verification solutions spanning the complete design cycle, including simulation, emulation, advanced debug, static/formal verification, FPGA-based prototyping and virtual prototyping. Synopsys’ Verification Continuum combines best-in-class technology, verification IP, and advanced methodologies enabling users to address rapidly escalating SoC complexity, accelerate time-to-market, and bring innovative products to market sooner.