DVCon 2017 Verification Lunch Panel

DVCon 2017 Verification Lunch Panel Event

On March 1, 2017 Synopsys hosted a verification panel at DVCon. Piyush Sancheti (Synopsys) highlighted the next wave of verification innovation in Synopsys’ Verification Continuum Platform. Bruce Greene (Synopsys) provided an update on VCS Fine Grained Parallelism and the significant simulation performance increase it delivers. YC Wong (Broadcom) shared his insights on the past, present and the future of low power verification, and how Synopsys solutions helped drive the turnaround time for low power signoff TAT from weeks to days.


Piyush Sancheti

Synopsys Verification Update
Senior Director of Marketing, Verification Group, Synopsys

Bruce Greene

VCS Fine-Grained Parallelism Technology
Principal Corporate Applications Engineer, Verification Group, Synopsys

YC Wong

Low Power SoC Verification: The Past, The Present & The Future
Sr. Technical Director and Distinguished Engineer, Broadcom

Piyush SanchePiyush Sancheti, Bruce Greene, & YC Wong DVCon Verification Lunch Presentersti, Bruce Greene & YC Wong
DVCon 2017 Verification Lunch Panel Event