DAC 2015 Verification Lunch Panel

DAC 2015 Verification Lunch Panel Video

SoC Leaders Verify with Synopsys

On June 9, 2015, Synopsys hosted a lunch event at DAC in San Francisco, CA. Michael Sanie highlighted the Synopsys Verification Continuum and several key next-generation technologies. Later, a panel of SoC industry experts from Altera, AMD, ARM, Cavium and Freescale share viewpoints on managing the growing verification complexity and how their leading SoC design teams have achieved success by collaborating with Synopsys.


Michael Sanie

Next-Generation Verification Technologies 
Michael Sanie, Senior Director, Verification Marketing


Carlos Velasco

SoC FPGA: What a Monster!
Carlos Velasco, Senior Manager, SoC Design Verification Group


Alan Hunter

Enabling Partner "Shift Left"
Alan Hunter, Senior Principal Design Engineer


Jim Ellis

Addressing Unique Verification Challenges of ThunderX ARM Processors
Jim Ellis, Director of Engineering


Alex Starr

Rethinking AMD's Cost of Verification
Alex Starr, Fellow & Pre-Silicon Solutions Architect


Robert Oshana

It's the Software, Stupid
Robert Oshana, Director of Software R&D, Digital Networking