Various languages can be used for the transaction-based testbench:
- C/C++/SystemC testbench: ZeBu transactors are adapted from the SCE-MI standard and follow a simplified/optimized API so you can be up and running with only a few lines of code. An API fully-compliant with SCE-MI is also available if compatibility across emulation platforms is more important than performance.
- SystemVerilog testbench: ZeBu transactors can be integrated with SystemVerilog testbenches using the ZeBu API, the standard SystemVerilog DPI, a SystemVerilog class, and the Verification Methodology Manual (VMM) Hardware Abstraction Layer (HAL), also from Synopsys.
The ZEMI-3 Transactor Compiler from Synopsys also simplifies the creation of transactor FSMs, and has the added benefits of:
- Supporting behavioral Verilog constructs, such as implicit state machines, wait states and mixed clock edges
- Automatic implementation of the transactor communication infrastructure
- Performance optimization via streaming and prefetching