ProtoLink

Simulation-Like Debug Solution for Multi-FPGA Prototype Boards

ProtoLink™ is an innovative simulation-like debug solution for multi-FPGA prototype boards. It provides simulator-like visibility and fast debug turnaround time for both HAPS FPGA-based prototyping solutions and custom FPGA prototype boards. ProtoLink allows you to:

  • Cut prototype debug time in half
  • Improve verification efficiency for early validation of SoC designs
  • Maximize ROI with faster and earlier development

Accelerate Prototype Board Verification

ProtoLink uses patented interconnect technologies and specialized software automation to bring the power of the industry-leading Verdi® Automated Debug System to the prototype board. This unique combination creates a new paradigm for rapid prototype verification that enables board developers and SoC design teams to:

  • Gain real-time visibility into thousands of signals for millions of cycles
  • Add/change probes in just minutes with fast probe ECO flow
  • Debug designs on prototype boards at the RTL level
  • Seamlessly debug designs across multiple FPGAs/Boards
  • Gain full visibility and control signals with force/release capabilities

Increase Design Visibility

ProtoLink provides a flexible FPGA prototype debug methodology that overcomes the limited visibility, difficult to use and cost barriers of traditional debug approaches. It uses intuitive, software-based methods to achieve a high level of design visibility that:

  • Expands the number of probe signals from 10s to 1000s with user-friendly time-division multiplexing (TDM) technology
  • Supports multiple probe groups and probe buses for viewing up to 16K signals per FPGA per probe group at one time
  • Deploys Siloti™ Visibility Automation System, if desired, to determine minimum set of probe signals needed for optimal design visibility

Reduce Debug Turnaround Time

ProtoLink makes FPGA prototype boards easier to debug starting at the RTL design stage all the way through final implementation. It shares the same compiling technology and design knowledge database as the Verdi debug platform to:

  • Ease RTL debug with advanced visualization, tracing and analysis capabilities
  • Drag-and-drop probe signals between Verdi and ProtoLink environments
  • View waveforms and set event/triggers across multiple FPGAs to analyze design behavior and identify the root cause of bugs
  • Add/change probes with fast probe ECO flow to eliminate long recompile and debug loops
  • Maintain RTL-to-gate correlation throughout the prototype implementation flow

Comprehensive, Easy to Use

ProtoLink automates FPGA setup, probe instrumentation, and interface tasks. Its hardware-independent architecture enables out-of-the-box operation with HAPS FPGA-based prototyping solutions or custom prototypes, and eases the transition to next-generation boards with the latest FPGA technologies.

Core Features

  • Synchronous and asynchronous sampling with small-footprint hi-speed transport IP on each FPGA
  • Probe data captured and uploaded into FSDB for debugging
  • Single design compilation to use ProtoLink and Verdi debug software
  • Probe memory stores up to 134M cycles (~1 second of emulation time) without using FPGA resources
  • Probe ECO with integrated revision management system saves hours of setup time
  • Flexible hardware kit links prototype board with engineering workstation to run conventional in-circuit emulation
  • Optional add-on module for Xilinx FPGA to do full visibility dumping and force/release for pre-selected signals