CustomSim Reliability Analysis

Analysis of post-layout parasitic effects and device reliability

Complete signoff verification of your circuit design requires much more than simulating the schematic netlist to ensure that it is functionally correct. To achieve predictable success, you must account for the true post-layout effects on power/ground busses and signal nets, and guarantee reliability against electromigration that can destroy narrow nanometer interconnect. With gate dielectrics now just a few atoms thick, the aging effects of hot carrier injection and negative-bias temperature instability must also be taken into account. CustomSim provides a complete set of analysis tools for device-level and interconnect reliability analysis; including IR drop, current density and electromigration, and device aging.

Overview

In order to reduce the risk of expensive mask changes and silicon re-spins; the signoff process for today's designs must account for the impact of parasitic devices on timing, power and reliability. These effects can only be accurately analyzed post-layout, by extraction and back-annotation of potentially tens or hundreds of millions of elements, which can easily exceed the capacity of competitor's FastSPICE simulators. CustomSim provides a complete set of tools for analyzing the impact of IR drop in power and ground busses, coupling effects in signal interconnect, and potential reliability failures from electromigration. 

MOS Reliability Analysis

Fragile nanometer transistors are stressed by high field strengths in the device channel, by high temperature, and by high-frequency switching activity over extended periods of time. These stress effects lead to device 'aging', resulting in performance degradation and designs that fail to meet specification during their expected operating life. CustomSim allows users to add aging effects to industry-standard BSIM3 and BSIM4 models. CustomSim enables users to measure performance degradation over time, by comparing the results of pre-stress and post-stress simulation results. 

Power Net Analysis: Static Power Net Resistance

Before performing a complete dynamic simulation for measurement of IR drop effects, a quick DC analysis of power and ground bus resistance can be used to catch gross errors such as missing vias and undersized metallization. CustomSim determines the resistance from each external power pad connection to the power pins of internal blocks, generating text reports and GDSII resistance maps for graphical visualization of power and ground bus resistance through all metal and via layers.

Power Net Reliability Analysis

CustomSim has the capability for analysis of IR drop and electromigration in power and ground busses, while simultaneously accounting for the effects of interconnect resistance on dynamic circuit performance. The unique direct-coupled methodology provides highly accurate measurement of power bus currents, by performing full circuit simulation in the presence of back-annotated parasitics. CustomSim overcomes the limitations of simulation with millions of extracted parasitic resistors, by incorporating built-in compression and reduction algorithms to maintain accuracy, capacity and performance.

In the proprietary methodology accurate transient current waveforms are acquired during dynamic simulation, and are used for detailed measurement of IR drop and current density in the complete, un-reduced power and ground nets. Other less-accurate approaches to power-net analysis estimate IR drop by characterizing cells before they are placed into a circuit layout, where the true in-silicon effects will be seen. Graphical output in GDSII and other formats allows designers to overlay results on their layout design for analysis and debug.