Analysis of post-layout parasitic effects and device reliability
Complete signoff verification of your circuit design requires much more than simulating the schematic netlist to ensure that it is functionally correct. To achieve predictable success, you must account for the true post-layout effects on power/ground busses and signal nets, and guarantee reliability against electromigration that can destroy narrow nanometer interconnect. With gate dielectrics now just a few atoms thick, the aging effects of hot carrier injection and negative-bias temperature instability must also be taken into account. CustomSim provides a complete set of analysis tools for device-level and interconnect reliability analysis; including IR drop, current density and electromigration, and device aging.