Download Brochure
Contact Us
Contact Us
Contact Us
Contact Sales
  • Company
  • About Us
  • Investor Relations
  • Community
  • Newsroom
  • Resources
  • Careers
Contact Us
All Synopsys
+ Silicon Design & Verification + Silicon IP + Software Integrity + About Us
Support
SolvNetPlus Software Integrity Customer Community
Global SItes
日本語 简体中文 繁體中文 Русский

CustomSim Circuit Check

CustomSim Circuit Check (CCK) helps users to avoid wasted simulation time by finding design and performance problems automatically, reporting potential problems in a circuit before running simulation. Circuit Check increases verification coverage and discovers potential trouble spots that simulation misses.

Parametric Checks

Circuit Check scans the netlist for common geometrical and electrical parameter errors:

  • MOSFET W, L, drain/source area, perimeter, tox
  • User limits can be set for each device model
  • Capacitor values
  • Simulation temperature
Parametric Checks

Design and Electrical Rule Checks

CCK finds hookup and bias errors before simulation:

  • Floating MOSFET gates
  • Forward-biased diodes, bulk nodes
  • No path to Vdd or GND
  • Shorted nodes: PMOS to GND, NMOS to Vdd

During simulation, CCK monitors:

  • Min/max voltages between nodes
  • Excessive element currents
  • Forward-bias conditions
Design and Electrical Rule Checks

Digital Logic/Memory Diagnostics

CCK prevents time-consuming debug problems:

  • Identifies un-initialized latches before transient simulation
  • Finds stuck-at nodes
  • Reports excessive stack-up of NMOS, PMOS devices

CCK traces logic paths:

  • Interactive debug mode
  • Finds the source of state changes
Digital Logic/Memory Diagnostics

Timing Checks

CCK performs static transistor-level timing analysis:

  • Computes Elmore delays
  • Measures rising paths to Vdd, falling paths to GND

Dynamic timing analysis:

  • CCK traces all path delays between source and target nodes
Timing Checks

Signal Integrity

CCK static crosstalk analysis:

  • Measures delay paths connected to floating parasitic capacitors
  • Calculates potential noise glitch
  • Identifies fast falling paths and slow rising paths
Signal Integrity

Low-Power Design and Leakage Detection

Find DC leakage:

  • Static check reports any path leaking current between voltage sources

Monitor standby current during simulation:

  • Detects potential leakage paths from multiple power supply domains
  • Identifies high-Z nodes, tests for leakage to GND/Vdd
Low Power Design and Leakage Detection

Synopsys and Samsung Release Certified 3nm Gate-All-Around AMS Design Reference Flow for Early Design Starts

Synopsys and Samsung Deliver Optimized iPDKs for Advanced Custom Design

Synopsys Collaborates with TSMC to Accelerate 3nm Innovation, Enabling Next-Generation SoC Design

Article

Low Power Meets Variability at 7/5nm

Accelerating Fault Campaign TAT Using Sampling Techniques

Ensuring Safety in Automotive IC Designs – TestMAX CustomFault

Solving Mixed-Signal Challenges using AMS Co-simulation with VCS

Tech Talk: Analog Fault Simulation for Automotive Designs

SNUG Silicon Valley 2019 Videolog: Accelerating Robust Custom Design

HSPICE SIG 2019 Video: Accelerating Robust Verification for Advanced Node Designs

White Papers

Machine Learning: Enabling Self-Optimizing Design Platforms for Better End-to-End Results

Custom Compiler Video Whitepapers

Synopsys TestMAX CustomFault: Redefining Analog Fault Simulation

Super Chips: TMC BiCS FLASH Memory

Super Chips: Renesas R-Car V3H SoC

HSPICE Webisode Series: Quick tips on S-element, eye diagrams, IBIS-AMI, RUNLVL, Monte Carlo, MOSRA and more!

VERIFICATION SOLUTIONS

Articles
Datasheets
Events
News
Success Stories
Tools
Videos
Webinars
White Papers