What's New in HSPICE

HSPICE M-2017.03 – Major Enhancements in March 2017 Release

Environment

• GUI support in the Simulation and Analysis Environment (SAE) for Modified Distribution,
  Q-Q plot

Fundamentals

• 1.5X core engine speed-up for large post-layout designs in advanced nodes
• Monte Carlo simulation with modified distribution for more efficient design regression by generating more samples in desired sections of distribution
• >3X speed-up of Shooting Newton-based phase noise analysis in large post-layout designs
• Support of Shooting Newton AC (SNAC) analysis for oscillators
• Enhanced transient noise analysis through improved flickering noise modeling

Signal Integrity

• Support of 4-level Pulse Amplitude Modulation (PAM-4) for eye diagram simulation: automatic bit stream generation, transient analysis, and StatEye in transient and convolution modes
• Rational function modeling turned on by default for S-element-based transient analysis

New Models

• BSIM-CMG 110
• BSIM-IMG 102.7, 102.8
• UTSOI 2.2
• PSP 103.4
• HiSIM2 280, 290
• HiSIM_HV 2.32
• HICUM L0 1.32
• HICUM L2 2.34

HSPICE L-2016.03 – Major Enhancements in March 2016 Release

Environment

• A native Simulation Analysis Environment to set up, manage, and monitor simulations and post-process simulation results for analog verification productivity improvement

Fundamentals

• 1.5X core engine speed-up for large post-layout designs in advanced nodes
  
• Improved MOSFET aging simulation with Monte Carlo both for fresh and aged circuits
• Support of built-in MOSRA Level 3 model for MOSFET HCI and BTI effects with partial recovery
• Support of .HBAC with .HBOSC analyses to enable large-signal periodic AC analysis for autonomous circuits

Signal Integrity

• Enhanced rational function modeling of S element with embedded decoupling/blocking capacitors to improve time-domain simulation
• Built-in support of decision feedback equalizer (DFE) in P element to enable early-stage exploration of high-speed link designs
• Enhancement of StatEye analysis to support IBIS-AMI mid-channel repeater flows
• HSPICE integration in the Channel Simulation and Analysis feature of Custom WaveView ADV for GUI-based setup and analysis of serial link designs

New Models

• BSIM-CMG 109
  
• BSIM-IMG 102.6.1
• BSIM6 6.1.1
• CMC_Diode 2.0
• EKV 3.0
• HiSIM_HV 2.30, 2.31
• MOSVAR 1.3

HSPICE 2015.06 – Major Enhancements in June 2015 Release

Fundamentals

• 1.5X speed-up in transient analysis of large post-layout designs, with single- or multi-core
• 1.5X speed-up in transient analysis of I/O/Macro cell
• Block-specific transient noise analysis to improve simulation performance and enable efficient design exploration
• 16nm/14nm/10nm FinFET ready

Signal Integrity

• 3X scalability on four cores on Windows for SI designs (now on par with Linux)
• 2X speed-up in linear network analysis and AC analysis of multi-million-element designs
• RATIONAL_FUNC support of S-parameters for AC analysis

New Models

• BSIM-CMG 108
• BSIM-IMG 102.5, 102.6-beta
• UTSOI 1.14k, 2.1f
• HiSIM_HV 2.2
• HICUM 2.33
• EKV 3.0

HSPICE 2014.09 – Major Enhancements in September 2014 Release

Fundamentals

• 2X faster throughput of standard cell library characterization with SiliconSmart compared to 2013.12 release
• 1.5X faster simulation of standard I/O and macro cells compared to 2013.12 release
• Robust DC convergence and improved runtime for 16nm and below

Signal Integrity

• IBIS 6.0 support

New Models

• BSIM-CMG 108 beta3
• BSIM 6.1 beta4
• BSIMSOI 4.5
• BSIM-IMG 102.3
• PSP 103.3
• MOSVAR 1.2

HSPICE 2013.12 – Major Enhancements in December 2013 Release

Fundamentals

• BSIM-CMG model evaluation runs 50% faster than the 2013.03 release, enabling faster simulation of FinFET circuits. This applies to both built-in and Verilog-A BSIM-CMG models
• Users can specify different RUNLVL values for different subcircuits and instances in the design hierarchy, enabling the speed-up of non-critical blocks, such as digital control, without compromising overall accuracy
• Users can run Monte Carlo analysis of SRAM bit cells using one billion samples distributed over multiple CPUs on the network. The Monte Carlo results are achieved using accurate SPICE Monte Carlo and can be used as a golden reference to verify the results of fast Monte Carlo methods
• 1.5X faster simulation of large post-layout circuits compared to 2013.03 release

Signal Integrity

• 1.5X speed-up of S-elements with over 100 ports, enabling faster transient analysis of large-scale systems, such as complex IC packages. The feature is qualified up to 600 ports

New Models

• FinFET BSIM-CMG 1.07 (level 72)
• BSIM6 6.0, 6.1beta2 (level 77)
• BSIM 4.8 (level 54)
• UTSOI 1.14f, 2.00g (level 76)
• PSP103.2 w/I self-heating (level 69)
• HiSIM-HV 1.24
• HiSIM-HV 2.10
• HICUM 1.31, 2.32
• Mextram 504.10.1, 504.11

MOS Reliability Analysis (MOSRA) now supports FinFET BSIM-CMG models

Documentation

• Users can use the "-help" option from the command line to access the online help topics

HSPICE 2012.06 – Major Enhancements in June 2012 Release

HSPICE for Analog

• Harmonic Balance analysis now supports multi-threading to deliver up to 4X speed up on 8 cores, enabling fast and accurate steady state analysis

Signal Integrity

• New S-element implementation speeds up the transient analysis of long-delay systems such as backplane traces and HDMI cables. Simulation of long bit patterns (e.g., 60,000 bits) can be up to 60X faster than 2011.09 release with no compromise of HSPICE golden accuracy

Multi-technology Simulation

• Multi-technology simulation (MTS) allows the simulation of different chips of different technologies in the same run without modifying the netlist, models or parameters of the individual chips. This technology will enable the simulation of 3D integrated circuits and silicon interposer packages.

New Models

• FinFET BSIM-CMG 105.031, 105.04, 106.0
• BSIM6
• HiSIM-HV 2.0.0
• Mextram 504.10

HSPICE 2011.09 – Major Enhancements in September 2011 Release

HSPICE for Analog

• HSPICE Precision Parallel technology extended beyond transient analysis to support transient noise, Monte Carlo, IBIS, and MOS reliability analysis (MOSRA)
• HPP technology now delivers 10X scaling on 16 cores

Distributed Processing

• Distributed processing now supports DC Monte Carlo analysis

Signal Integrity

• Parallel S-parameter evaluation improves HPP scaling on high-speed circuits
• W-element field solver now supports multi-threading, delivers 5X speed-up on 8 cores, enables faster analysis of complex traces at more frequency points
• Multiple edges support in StatEye analysis increases eye diagram accuracy for strongly nonlinear buffers

New Model Support

• BSIM 4.7
• BSIMSOI 4.4
• HICUM Level 0 1.3
• HICUM Level 2 2.3
• HiSIM 2.5.1
• HiSIM_HV 1.2.1, 1.1.2 and 2.0.0
• FinFET BSIM-CMG 105
• Support of CMC TMI2 modeling API

HSPICE 2010.12 – Major Enhancements in December 2010 Release

• HSPICE Precision Parallel (HPP) technology
  HPP is a new multi-threading technology that delivers up to 7X simulation speed-up for analog and mixed-signal designs. The technology scales effectively up to 8 cores and can handle post-layout circuits larger than 10 million elements. To learn more about HPP technology, please download the white paper.
• HSPICE distributed processing (DP)
  Improve the throughput of corner case analysis, Monte Carlo, and parametric sweeps by automatically distributing the job on a cluster of machines. Distribution takes place directly from an HSPICE netlist and does not require a third-party load-balancing infrastructure. The distributed processing throughput scales linearly with the number of CPUs, reaching 17X on 20 CPUs.
• Jitter measurement in HSPICE transient noise analysis
  Jitter is efficiently calculated in reasonable simulation times using either the Monte Carlo or Stochastic Differential Equations (SDE) method coupled with post-processing in Custom WaveView. The overall performance of transient noise analysis in the 2010.12 release has improved 3X over the previous release. The overhead of running transient noise analysis is only 3X a plain transient run.
• New selective-net back-annotation flow
  The flow significantly improves post-layout simulation performance by attaching parasitics only to active nets in the design. Active nets are automatically identified using the active net check in CustomSim.
• Statistical analysis
  ACMatch, DCMatch and advanced Monte Carlo analysis, originally available with the Variation Block, now also support the traditional HSPICE parameter distribution functions (e.g., AGAUSS).

Signal Integrity

• 3X field solver performance improvement, enabling faster analysis of complex traces at more frequency points
• Graphical visualization of W-element cross sections
• Unfolding of statistical eye diagrams to examine the waveforms and analyze crosstalk at specific time points
• Touchstone 2.0 support. enabling native mixed-mode S-parameter support and explicit frequency sampling point declaration
• Support of HSPICE parameters in IBIS 5.0 Algorithmic Modeling Interface (AMI), enabling sweep and parametric analysis of AMI models

New syntax and models 

• BSIM-CMG 104.0
• BSIMSOI 4.3.1
• HICUM 2.24
• Support for case-sensitive netlist formats

HSPICE 2010.03 - Major Enhancements in March 2010 Release

Performance, Convergence, Capacity & Accuracy Improvements

• Improved single-core & multi-threaded runtime performance on large pre- and post-layout circuits
  • 2X on 1 core + scaling to 8 cores

Analog/RFIC Design

• Loop stability analysis
• Enhanced back-annotation flow
• Design for yield—extended variability analysis

Signal Integrity

• IBIS 5.0—AMI support in Statistical Eye Diagram (.StatEye)

New Model Support

• BSIM 4.6.5
• BSIM SOI 4.2
• HSIM_HV 1.2.0

HSPICE 2009.09 - Major Enhancements in September 2009 Release

Performance, Convergence, Capacity & Accuracy Improvements

• Improved DC auto convergence for analog circuits
• Improved runtime performance on standard cells and large pre- and post-layout circuits
• Improved capacity: Up to 5M Elements with 500K MOS

Usability

• HSPICE & HSPICE RF integration (single binary solution)
• Simplified log file with improved error/warning messages king

Analog/RFIC Design

• Integration with Synopsys' Custom Designer's Simulation & Analysis Environment
• Improved Analog.lib, RF.lib and PDK support for HSPICE within Cadence™ Virtuoso®
• Transient Noise Analysis – Phase 2: Stochastic Differential Equation (SDE) approach

Signal Integrity

• Statistical Eye Diagram (.StatEye) Enhancements

New Model Support

• MOSRA reliability model enhancements
• MOSFET: BSIM4.6.4, PSP 103.1, BSIMSOI 4.1, HiSIM 2.5.0, HiSIM_HV v1.1.1
• BJT: HICUM L2 v 2.23 & L0 v 1.2

HSPICE 2009.03 - Major Enhancements in March 2009 Release

Performance, Convergence, Capacity & Accuracy Improvements

• Improved DC auto convergence
• Improved runtime performance & multi-threading scalability on large circuits

Usability

• Store/restore capability
• Improved ".lis" reporting
• Improved error/warning messages & syntax checking

Analog/RFIC Design

• HSPICE integration to Synopsys' Custom Designer™
• HSPICE integration to the Cadence™ Virtuoso® Analog Design Environment - RF and Monte Carlo support
• Transient Noise Analysis – Phase 1: Monte Carlo-based approach

New Model Support

• BSIM 4.6.2 & 4.6.3
• BSIM SOI 4.1
• Mextram 504.7

HSPICE 2008.09 - Major Enhancements in September 2008 Release

Performance, Convergence & Accuracy Improvements

• Distributed Monte Carlo analysis & sweeps
• Improved bisection algorithm
• Improved DC auto convergence

Cell Characterization

• 4X Faster Liberty NCX with HSPICE (compared to Sept 2007)

ADC & DAC Characterization

• High accuracy FFT analysis & measurement enhancements

Signal Integrity

• Statistical Eye Diagram (.StatEye)

RFIC & High Speed PLL

• Automated Accumulated Jitter Analysis

New Model Support

• Enhanced CMI/TMI model support
• Enhanced MOSRA model (NBTI/HCI device aging / reliability analysis)
• HiSIM-HV high voltage MOS model

HSPICE 2008.03 - Major Enhancements in March 2008 Release

Performance, Convergence & Accuracy Improvements

• 3X faster on 1 CPU and over 6X faster on 4 CPUs for large post layout designs
• Improvements to auto convergence algorithms
• Supports WDF format for rapid large wave form loading & viewing in WaveView Analyzer

New Cadence ADE Integration

• Built and supported by Synopsys
• Supports all major HSPICE analysis
• User interface adapted for HSPICE
• Cross probing, back-annotation, and much more

Post Layout

• 3X faster on 1 CPU and over 6X faster on 4 CPUs for large designs (> 50000 elements)
• 2X reduction in memory requirements

Signal Integrity

• Standalone S-element builder
• S-parameter passivity enforcement

RF - Automated Accumulated Jitter Analysis

• Behavioral noise analyses of linear phase-domain equivalent circuits that may include phase noise as input stimuli
• Predict closed-loop PLL phase noise based on block-level noise contributions.
• Calculate Timing Jitter or N-Cycle Jitter responses based on phase noise inputs.
• Examine the impact on phase noise frequency response due to feedback loop design changes.

New Model Support

• HiSIM LDMOS100-SC3, PSP 102.2, MOS20 2002.2
• MOSRA API: Reliability analysis for modeling device degradation due to hot carrier injection (HCI) and negative bias temperature instability (NBTI)

HSPICE 2007.09 - Major Enhancements in Sept 2007 Release

Performance, Convergence & Accuracy Improvements

• Multi-CPU .ALTER support
• Improved auto convergence
• Faster netlist read-in

Design for Yield - Variability Analysis

• Spatial variation support
• Subcircuit parameter support

Board & Package Design - Signal Integrity

• IBIS time step control improvement

HSPICE RF – RFIC & High Speed PLL design

• S-element support in Shooting Newton for spiral inductor modeling
• Spurious noise analysis

Post Layout

• SPEF & DSPF support

New Device Model Support

• HiSIM 2.4

HSPICE 2007.03 - Major Enhancements in March 2007 Release

Performance & Usability Improvements

• Parser & error check runtime & memory improvements
• Error messaging improvements with line number printout

Design for Yield - Variability Analysis

• ACMATCH for mismatch analysis in AC
• Interconnect variation analysis with StarRC

Board & Package Design - Signal Integrity

• S-element Performance Improvement
  • Recursive convolution for huge (500 port) S-parameter input
• S-element Accuracy Enhancements
  • Improved DC point prediction
• IBIS 4.2

PLL & VCO Design – Analysis with HSPICE RF

• SNNOISE strobing, displays noise spectrum at a specific time point
• Improved output, phase noise output by source
• Complete PLL jitter methodology (example & white paper)
  • Uses Harmonic Balance & Shooting Newton

New Device Model Support

• BSIM 4.6.0
• PSP 102.1
• HiSIM 2.3.1
• MOS reliability analysis model – NBTI & HCI

HSPICE 2006.09 - Major Enhancements in Sept 2006 Release

Performance Improvements

• Transient time step improvement (RUNLVL option turned on by default)
• 20% speedup for Linux
• Multithreading improvement
• Improved matrix handling for large and extracted circuits
• 64-bit Linux (all Linux platforms, including RedHat/Opteron, SUSE/EM64T)

Design for Yield

• Variability Analysis:
  • Smart Monte Carlo – Latin Hypercube Sampling
• 65nm WPE model enhancement

Signal Integrity – Board & Package Design

• W-element speed and accuracy improvements:
  • Improved time-step control
  • Special handling for high dielectric loss
  • Output of impedance values
  • Faster 2D EM cross-sectional analysis (3x-5x speedup)
• S-Parameter data interpolation improvement:
  • Capture high-frequency resonance effects

HSPICE RF

• Time-domain steady-state simulation (Shooting Newton):
  • Faster simulation for RF circuits with digital logic
  • (phase/frequency detectors, dividers, ring oscillators)
  • Small-signal transfer and noise analyses

Documentation

• HSPICE - -help command line invocation for easy access and quick search of the HSPICE – HSPICE RF Command Reference

Would you like more information?

To see all the capabilities and models supported in HSPICE, please click here.

To obtain the latest release of HSPICE, please download the HSPICE binaries and the HSPICE release notes, both found on SolvNet.