SystemVerilog Verification Using UVM 1.2

Overview

In this hands-on workshop, you will learn how to develop a UVM 1.1 and UVM 1.2 SystemVerilog testbench environment which enables efficient testcase development. Within the UVM environment, you will develop stimulus sequencer, driver, monitor, scoreboard and functional coverage. Once the UVM environment has been created, you will learn how to easily manage and modify the environment for individual testcases.
You will learn how to use the configuration database to control both, component behavior and stimulus generation. You will use the power of Object-oriented programming to easily replace component and transaction objects with their derived-class variations. You will learn how to use callbacks to increase the controllability and observability of the testbench. You will also learn how to model registers in UVM that simplify the configuring and testing the registers in your device.
 

Objectives

At the end of this workshop the student should be able to:

  • Develop UVM 1.1 and UVM 1.2 tests
  • Implement and manage report messages for printing to terminal or file
  • Create random stimulus and sequences
  • Build and manage stimulus sequencers, drivers and monitors
  • Create configurable agents containing sequencer, driver and monitor for re-use
  • Create and manage configurable environments including agents, scoreboards, TLM ports and functional coverage objects
  • Implement a collection of testcases each targeting a corner case of interest
  • Create an abstraction of DUT registers and manage these registers during test, including functional coverage and self-test
     

Audience Profile

Design or Verification engineers who develop SystemVerilog testbenches using UVM 1.1 and UVM 1.2 base classes.
 

Prerequisites

To benefit the most from the material presented in this workshop, students should have completed the SystemVerilog Testbench workshop.
 

Course Outline

Day 1

  • SystemVerilog OOP Inheritance Review
    • Polymorphism
    • Singleton Class
    • Singleton Object
    • Proxy Class
    • Factory Class
  • UVM Structural Overview
    • Key Concepts in UVM: Agent, Environment and Tests
    • Implement UVM Testbenches for Re-Use across Projects
    • Code, Compile and Run UVM Tests
    • Inner Workings of UVM Simulation including Phasing
    • Implement and Manage User Report Messages
  • Modeling Stimulus (UVM Transactions)
    • Transaction Property Implementation Guidelines
    • Transaction Constraint Guidelines
    • Transaction Method Automation Macros
    • User Transaction Method Customization
    • Use Factory Override to Control Transaction Constraints
  • Creating Stimulus Sequences (UVM Sequence)
    • Implementing User Sequences
    • Using UVM Macros to create and manage Stimulus
    • Explicitly Execute Sequences in Test
    • Implicitly Execute Sequences Through Configuration in Environment
    • Sequence Execution Protocol
    • Phase Objection

Day 2

  • Component Configuration and Factory
    • Establish and Query Component Parent-Child Relationships
    • Set Up Component Virtual SystemVerilog Interfaces with uvm_config_db
    • Constructing Components and Transactions with UVM Factory
    • Implement Tests to Configure Components
    • Implement Tests to Override Components with Modified Behavior
  • TLM Communications
    • TLM Push, Pull and Fifo Modes
    • TLM Analysis Ports
    • TLM Pass-Through Ports
    • TLM 2.0 Blocking and Non-Blocking Transport Sockets
    • DVE Waveform Debugging with Recorded UVM Transactions
  • Scoreboard & Coverage
    • Implement scoreboard with UVM In-Order Class Comparator
    • Implement scoreboard UVM Algorithmic Comparator
    • Implement Out-Of-Order Scoreboard
    • Implement Configuration/Stimulus/Correctness Coverage
  • UVM Callback
    • Create User Callback Hooks in Component Methods
    • Implement Error Injection with User Defined Callbacks
    • Implement Component Functional Coverage with User Defined Callbacks
    • Review Default Callbacks in uvm_sequence Base Class

Day 3

  • Advance Sequence/Sequencer
    • Implement Top Level Sequence and Sequencer to Manager Sequence Execution within Different Agents
    • Disable Selected Sequencer in Agents through the Sequencer's "default" Configuration Field
    • Implement uvm_event for Synchronization of Execution among Sequences in the Top Level Sequence
    • Implement Grab and Ungrab in Sequences for exclusive access to Sequencer
  • Phasing and Objections
    • Managing Objections within Component Phases
    • Implement Component Phase Drain Time
    • Implement Component Phase Domain Synchronization
    • Implement User Defined Domain and Phases
    • Implement UVM Phase Jumping
  • Register Layer Abstraction (RAL)
    • DUT Register Configuration Testbench Architecture
    • Develop DUT Register Abstraction (.ralf) File
    • Use ralgen Utility to Create UVM Register Model Class Files
    • Create UVM Register Adapter Class
    • Develop and Execute Sequences Using UVM Register Models
    • Use UVM Built-In Register Test Sequences to Verify DUT Register Operation
    • Enable RAL Functional Coverage
  • Summary
    • Review UVM Methodology
    • Review Run-Time Command Line Debug Switches
       

Synopsys Tools Used

  • VCS 2017.03
  • Verdi 2017.03