A hands-on introduction to use VCS-NLP to run and debug power-aware simulations on RTL code instrumented with power intent defined using IEEE-1801 (aka UPF).
This course teaches the key features of the SystemVerilog Assertion language and its use in VCS, including how to create reusable, scalable assertions and assess the effectiveness of your testbench.
This course provides a hands-on introduction to the SystemVerilog language to verify a device under test using VCS with object-oriented methodologies targeting coverage-driven constrained-random test environments.
In this course, you will learn how to build EDA industry standard UVM 1.1 and UVM 1.2 testbenches. It is recommended that you take the SystemVerilog Testbench workshop before this class.
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