StarRC

Overview

In this workshop, you will learn the fundamentals of RC extraction using StarRC. You will start by understanding the various stages of extraction. You will see the different commands for the Milkyway, LEF/DEF and NDM gate level flows. You will learn how to run the Simultaneous Multi Corner (SMC) flow to generate data for multiple process corners with a single run. You will see how to generate parasitic data in the Galaxy Parasitic Database (GPD) output format. Next, you will learn the LVS setup and extraction flow for transistor level designs using IC Validator.  Users are introduced to the field solver (Rapid3D) flow which can be used for extracting critical nets at a very high level of accuracy.

Users will learn how to write an Interconnect Technology File (ITF) to model the foundry process. You will see how to generate specific netlists for different analysis such as clock net, crosstalk and power analysis. Practical issues such as metal fill and PCELL handling will also be discussed.

Users will be shown how to debug databases that have shorts and opens. 

Objectives

At the end of this workshop the student should be able to:

  • Understand the fundamentals of extraction
  • Set up and perform RC extraction
  • Understand the different gate level flows
  • Perform transistor level extraction based on the IC Validator flow
  • Understand the field solver flow and usage
  • Write a process file to generate a process model
  • Perform extraction using the different selective net listing methods and reliability verification methods
  • Understand extraction with real and emulated metal fills

Audience Profile

Designers or process technologists who need to perform signoff extraction

Prerequisites

To get the most out of this workshop, the following are suggested but not required:

  • Familiarity with place and route tools and flows
  • Familiarity with transistor level tools and flows
  • Familiarity with physical design verification tools

Course Outline

Day 1

  • Extraction Fundamentals
  • Gate Level Extraction
  • Transistor Level Extraction
  • Selective Net listing

Day 2

  • Field Solver
  • Process Modeling
  • Metal Fill

Synopsys Tools Used

  • StarRC, O-2018.06
  • IC Validator, O-2018.06