In this workshop, you will learn the fundamentals of RC extraction using StarRC. You will start by understanding the various stages of extraction. You will see the different commands for the Milkyway, LEF/DEF and NDM gate level flows. You will learn how to run the Simultaneous Multi Corner (SMC) flow to generate data for multiple process corners with a single run. You will see how to generate parasitic data in the Galaxy Parasitic Database (GPD) output format. Next, you will learn the LVS setup and extraction flow for transistor level designs using IC Validator. Users are introduced to the field solver (Rapid3D) flow which can be used for extracting critical nets at a very high level of accuracy.
Users will learn how to write an Interconnect Technology File (ITF) to model the foundry process. You will see how to generate specific netlists for different analysis such as clock net, crosstalk and power analysis. Practical issues such as metal fill and PCELL handling will also be discussed.
Users will be shown how to debug databases that have shorts and opens.
At the end of this workshop the student should be able to:
Designers or process technologists who need to perform signoff extraction
To get the most out of this workshop, the following are suggested but not required:
Day 1
Day 2