In this workshop, you will learn to use TestMAX Advisor (previously known as SpyGlass DFT) to perform RTL testability analysis that will allow you to fine-tune your RTL early in the design cycle. This will verify the design scan readiness and Test Robustness and work towards meeting fault and test coverage goals. The workshop introduces basic DFT principles and explores essential techniques to setup runs. It will explain the various audit reports and how to use them when analyzing the design. It will also show how to use the GUI for debug of violations and explain various annotations seen on schematics. It will also cover running transition At-speed coverage audit as well as random resistant fault analysis. To complete the flow, it will also cover how to run connectivity check feature.
At the end of this workshop you should be able to:
Design and Test engineers who need to identify and fix DFT violations in their RTL to ensure a successful scan insertion into multi-million gate SoCs, and ensure high test coverage results in ATPG.
There are no prerequisites for this workshop. Prior experience with Design Compiler, other SpyGlass products and writing Synopsys Tcl scripts is useful, but not required.
In this two-day course, students will learn the key features and benefits of using TestMAX Advisor to perform RTL testability and coverage analysis.
Day 1
Day 2