SpyGlass DFT ADV

Overview

In this workshop you will learn to use SpyGlass DFT ADV to perform RTL testability analysis that will allow you to fine-tune your RTL early in the design cycle. This will verify the design scan readiness and Test Robustness and work towards meeting fault and test coverage goals. The workshop introduces basic DFT principles and explores essential techniques to setup SpyGlass DFT runs. It will explain the various audit reports and how to use them when analyzing the design. It will also show how to use the GUI for debug of violations and explain various annotations seen on schematics. It will also cover running transition At-speed coverage audit as well as random resistant fault analysis. To complete the flow, it will also cover how to run connectivity check feature.

Objectives

At the end of this workshop you should be able to:

• Setup a project file and SGDC file to run a basic testability check
• Run the goal and analyze the results using GUI and reports
• Recognize common design constructs that cause typical DFT violations
• Suggest techniques to correct certain DFT violations
• Run transition delay coverage audit
• Explore your design for Random Resistant Faults and learn how to add test points
• Explore different test points that could be added to improve testability and links to Physically aware DFTMAX flow
• Use SpyGlass DFT to verify scan chains in a scan inserted netlist
• Learn how to write a script to check on connectivity requirements of your design to verify integration of netlist at top level

Audience Profile

Design and Test engineers who need to identify and fix DFT violations in their RTL to ensure a successful scan insertion into multi-million gate SoCs, and ensure high test coverage results in ATPG.

Prerequisites

There are no prerequisites for this workshop. Prior experience with Design Compiler, other SpyGlass products and writing Synopsys Tcl scripts is useful, but not required.

Course Outline

In this intensive, one-day course, students will learn the key features and benefits of using VCS-NLP to perform power-aware functional simulations.

Day 1

• Introduction to DFT Principles
• Introduction to SpyGlass DFT Flow
• Early Testability verification and Reports
• Debug using the GUI
• Transition Delay Checks
• Random Resistant Fault Analysis and Test Points
• Post stitch DRC Checks
• Connectivity Checks
• Conclusion and Customer Support  

Synopsys Tools Used

• SpyGlass DFT ADV 2017.12-SP2